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Junction Yield Analysis for 10 V Programmable Josephson Voltage Standard Devices

Published

Author(s)

Anna E. Fox, Paul D. Dresselhaus, Alain Rufenacht, Aric W. Sanders, Samuel P. Benz

Abstract

Analysis of the Josephson junction yield in the National Institute of Standards and Technology 10 V Programmable Josephson Voltage Standard (PJVS) has been performed by fabricating and measuring over 25 million Nb/NbxSi1-x/Nb junctions. Using the 265,116 SNS junctions per PJVS device, it was possible to measure and then estimate the number single junction defects within these long arrays. This was accomplished by comparing IV curve data to models simulating various junction defect mechanisms. Understanding the source of junction defects in the fabrication process is important for maximizing yield and uniformity, both of which directly relate to the current margin of the quantized voltage step. We have recently yielded 34 PJVS devices of which 16 were free of defects, many with n=1 Shapiro step margins >2 mA. This involved fabricating high-yield wafers, the best of which had a defect density around 3 ppm across the wafer.
Citation
IEEE Transactions on Applied Superconductivity
Volume
25
Issue
3

Keywords

Programmable Josephson voltage standard, Josephson junctions, superconducting films, superconducting circuit fabrication, Superconductor-normal-superconductor devices, superconducting device fabrication, superconducting integrated circuits, Josephson devices, Josephson logic, Niobium, Superconducting devices, Superconducting device fabrication
Created December 5, 2014, Updated November 10, 2018