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Influence of Buffer Layer Thickness on Memory Effects of SrBi2Ta2O9 /SiN/Si Structures

Published

Author(s)

Jin-Ping Han, Sang-Mo Koo, Curt A. Richter, Eric M. Vogel

Abstract

We deposited 250 nm thick SrBi2Ta2O9 (SBT) thin films on silicon-nitride buffered Si (100) substrates to form metal-ferroelelctric-insulator-semiconductor (MFIS) structures and observed a significant influence of buffer layer thickness on the magnitude and direction of the capacitance-voltage (C-V) memory window. As the SiN buffer layer thickness was decreased from 6 nm to 2 nm, the C-V memory hysteresis direction changed from the ferroelectric polarization dominated memory direction (i.e., counter-clockwise for n-Si) to a trapping-related hysteresis direction (i.e., clockwise for n-Si). The memory windows for both cases exhibited similar temperature dependence. The memory window approached zero at 340-380oC, which corresponds to Curie Temperature (Tc) of the ferroelectric SBT films. When the temperature was returned to room temperature, the hysteresis windows are recovered. A detailed study has led us to believe that the switching of polarization of the ferroelectric SBT plays a key role in the observed temperature dependence, for both the ferroelectric polarization dominated and the trapping dominated memory window.
Citation
Applied Physics Letters
Volume
85
Issue
8

Keywords

Dielectric, ferroelectric, and piezoelectric devices

Citation

Han, J. , Koo, S. , Richter, C. and Vogel, E. (2004), Influence of Buffer Layer Thickness on Memory Effects of SrBi2Ta2O9 /SiN/Si Structures, Applied Physics Letters (Accessed April 25, 2024)
Created August 22, 2004, Updated October 12, 2021