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High coherence plane breaking packaging for superconducting qubits



David P. Pappas, Xian Wu, Nicholas T. Bronn, Salvatore B. Olivadese, Vivekananda P. Adiga, Jerry M. Chow


Wedemonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.
Quantum Science and Technology


Quantum Computing, Quantum Error Correction, Superconducting Circuits, Pogo Pins, Microwave Interconnects, Extensible Qubit Architecture, Qubit Coherence, Socket, Packaging


Pappas, D. , Wu, X. , Bronn, N. , Olivadese, S. , Adiga, V. and Chow, J. (2018), High coherence plane breaking packaging for superconducting qubits, Quantum Science and Technology, [online], (Accessed February 26, 2024)
Created February 7, 2018, Updated November 10, 2018