FPGA-based Low-Latency Digital Servo for Optical Physics Experiments

Published

October 22, 2020

Author(s)

Marco Pomponio, Archita Hati, Craig Nelson

Abstract

We propose a general-purpose dual-channel field-programmable gate array (FPGA) based digital servo with a minimum latency around 200 ns. This servo implements a proportional, dual- integration and derivative (PIID) controller along with internal numerical controlled oscillators (NCO), a phase detector (PD) utilizing a fast in-phase and quadrature (I/Q) detection algorithm (80 ns), NCO modulator, network analyzer, auto-locker, ramp generator, and low pass filters. A web interface and/or python commands over TCP/IP allows full control and monitoring. The servo has been successfully used to lock Pound-Drever-Hall cavities, phase- locked loops and optical frequency combs. A simple experiment phase-locking two dielectric resonator oscillators (DRO) has been set up to demonstrate a 1 MHz closed-loop bandwidth.

Proceedings Title

IEEE IFCS-ISAF 2020 Conference Proceedings

Conference Dates

July 19-23, 2020

Conference Location

Keystone, CO, US

Conference Title

IEEE IFCS-ISAF 2020 Conference

Pub Type

Conferences

Download Paper

https://doi.org/10.1109/IFCS-ISAF41089.2020.9234889

Local Download

Keywords

automatic locking, digital phase detector, digital servo, DRO, FPGA, low-latency, optical frequency comb

Citation

Pomponio, M. , Hati, A. and Nelson, C. (2020), FPGA-based Low-Latency Digital Servo for Optical Physics Experiments, IEEE IFCS-ISAF 2020 Conference Proceedings, Keystone, CO, US, [online], https://doi.org/10.1109/IFCS-ISAF41089.2020.9234889, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=930874 (Accessed October 4, 2025)