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Forward Issue on Electrochemical Processing of Interconnects

Published

Author(s)

Thomas P. Moffat, Daniel Josell

Abstract

On-going densification of microelectronics has driven the development of cost effective and reliable processes for fabricating circuitry ranging from nanometer scale trenches and vias for on-chip interconnects to micrometer scale through-silicon-vias (TSV) for emerging chip stacking applications. Decreasing dimensions of planar transistors through the 1980’s led to the need for building in 3-D that began to take hold in the 1990’s and then sharply accelerated with the introduction of the damascene process. The process derives its name from the damascening technique used by artisans from Toledo, Spain to Kyoto, Japan, where gold and silver were inlaid in oxidized steel plates to form intricate ornamental designs.^(1) However, it was developments at IBM culminating in a 1997 announcement that a combination of wet chemical methods, namely electroplating and chemical mechanical planarization (CMP), that enabled multilevel on-chip interconnects and thus 3-D circuitry of arbitrary complexity.^(2,3) Shrinking dimensions also required a change of material, from Al to Cu, to satisfy performance (conductivity) and reliability (electromigration) concerns.^(3) Copper interconnect technology on transistor laden 300 mm diameter Si wafers, like that shown Fig. 1, is now the coin of the microelectronics realm.^(4)
Citation
Journal of the Electrochemical Society
Volume
160
Issue
12

Keywords

copper, interconnects, superconformal

Citation

Moffat, T. and Josell, D. (2013), Forward Issue on Electrochemical Processing of Interconnects, Journal of the Electrochemical Society (Accessed June 21, 2024)

Issues

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Created December 10, 2013, Updated February 19, 2017