Boyar, J.
and Peralta, R.
(2011),
A depth-16 circuit for the AES S-box, IACR Cryptology ePrint Archive, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=908382, http://eprint.iacr.org/2011/332
(Accessed December 2, 2024)
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A depth-16 circuit for the AES S-box
Published
Author(s)
Joan Boyar,
Abstract
New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-box and its inverse, consisting of 63 gates.Citation
IACR Cryptology ePrint Archive
Volume
2011
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Keywords
AES, S-box, finite field inversion, circuit complexity, circuit depth.
Citation
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Created June 16, 2011, Updated October 12, 2021