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Custom Hardware to Eliminate Bottlenecks in QKD Throughput Performance

Published

Author(s)

Alan Mink

Abstract

The National Institute of Standards and Technology (NIST) high-speed quantum key distribution (QKD) system was designed to include custom hardware to support the generation and management of gigabit data streams. As our photonics improved our software sifting algorithm could not keep up with the amount of data generated. To eliminate this problem we implemented the sifting algorithm into our programmable chip (FPGA) hardware, gaining a factor of 50x improvement in the sifting capacity rate. As we increased the distance and speed of our QKD systems, we discovered a number of other performance bottlenecks in our custom hardware. We discuss those bottlenecks along with a new custom hardware design that will alleviate them, resulting in an order of magnitude increase in capacity of secret key generation rate.
Proceedings Title
SPIE Optics East | 2007 |
Conference Dates
September 9-12, 2007
Conference Location
Boston, MA
Conference Title
SPIE Optics East 2007

Keywords

Field Programmable Gate Array (FPGA), printed circuit board, privacy amplification, Quantum Key Distribution (QKD)

Citation

Mink, A. (2007), Custom Hardware to Eliminate Bottlenecks in QKD Throughput Performance, SPIE Optics East | 2007 |, Boston, MA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=51205 (Accessed July 20, 2024)

Issues

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Created September 5, 2007, Updated January 27, 2020