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Better Circuits for Binary Polynomial Multiplication

Published

Author(s)

Rene C. Peralta, Magnus G. Find

Abstract

We develop a new and simple way to describe Karatsuba-like algorithms for multiplication of polynomials over GF2. These techniques, along with interpolation-based recurrences, yield circuits that are better (smaller and with lower depth) than anything previously known. We use our optimization tools to actually build the circuits for n-term binary polynomial multiplication for values of n of practical interest.
Citation
IEEE Transactions on Computers
Volume
68
Issue
4

Keywords

Binary polynomial multiplication, circuits, symmetric bilinear circuits

Citation

Peralta, R. and Find, M. (2019), Better Circuits for Binary Polynomial Multiplication, IEEE Transactions on Computers, [online], https://doi.org/10.1109/TC.2018.2874662 (Accessed June 15, 2024)

Issues

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Created April 1, 2019, Updated May 1, 2019