Architecture of the NBS Pipelined Image Processing Engine
Ernest Kent, Michael O. Shneier, Ronald Lumia, M Herriman, R Luck, G Henrici
The Sensory-Interactive Robotics Group of the National Bureau of Standards is producing PIPE (Pipelined Image Processing Engine), an experimental, multi-stage, multi-pipelined image processing device for research in low-level machine vision. The device can acquire images from a variety of sources, such as analog or digital television cameras, ranging devices, and conformal mapping arrays. It can process sequences of images in real time, through a series of local neighborhood and point operations, under the control of a host device. Its output can be presented to such a devices as monitors, robot vision systems, iconic to symbolic mapping devices, and image processing computers. In addition to a forward flow of images through successive stages of operations as in a traditional pipeline, other paths between the stages of the device permit concurrent, interacting pipelining of image flow in other directions. In particular, recursive operations returning images into each stage, and feedback of the results of operations from each stage to the preceding stage are supported in this manner. This architecture facilitates a variety of relaxation operations, interactions of images over time, and other interesting functions. Numerous operations are supported; within each stage these include arithmetic and Boolean neighborhood operations on images. Between-stage operations on each pixel include thresholding, Boolean and arithmetic operations, functional mappings, and a variety of functions for combining pixel data converging via the multiple pipelined image paths. The device also implements several alternative processing modes. Some operate within each stage, for example to implement MIND operations specific to regions of interested defined by the host device or by previous operations on the image. Other operate between stages, for example to support variable resolution pyramids.
January 1, 1984
Algorithm-Guide Parallel Architectures for Automatic Target Recognition
, Shneier, M.
, Lumia, R.
, Herriman, M.
, Luck, R.
and Henrici, G.
Architecture of the NBS Pipelined Image Processing Engine, Algorithm-Guide Parallel Architectures for Automatic Target Recognition, Leesburg, VA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=820201
(Accessed December 4, 2023)