Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
While Boolean logic has been the backbone of information processing, there are computationally hard problems like solving constrained optimization problems wherein this conventional paradigm is fundamentally inadequate. This results in computational inefficacy, and motivates us to explore new pathways to their solution. In this talk, we introduce an experimental testbed comprising of compact coupled relaxation oscillator based dynamical system that exploits the insulator-metal transition in correlated oxide (for example VO2), to efficiently solve the vertex coloring of arbitrary graphs, a prototypical combinatorial optimization problem. Our work is inspired by the understanding that optimization finds a natural analogue in the energy minimization processes of highly parallel, coupled dynamical systems. Our work not only elucidates a physics-based computing method but also presents opportunities for building customized analog co-processors for solving computationally hard problems efficiently.
Sponsors
NSCI Committee
1:00 p.m. - 2:00 p.m. (Gaithersburg, Bldg. 221, Room B145)
11:00 a.m. - 12:00 p.m. (Boulder, VTC in 81-1A116)
Suman Datta
Notre Dame
Suman Datta is the Chang Family Chair Professor of Engineering Innovation at the University of Notre Dame. Prior to that he was a Professor at The Penn State University in Electrical Engineering from 2007 to 2011. Before joining Penn State, from 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, where he developed several generations of logic transistor technologies including high-k/metal gate, Tri-gate and non-silicon channel CMOS transistor technologies. His research interests are in novel solid-state materials and devices, fundamental understanding of electron transport, and very low-power circuit design. His group’s current focus is on intermittent computing powered by energy harvesters, collective computing using synchronized state of coupled systems and cognitive computing using artificial neurons and synapses. He was a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015). He is Fellow of IEEE and Fellow of National Academy of Inventors (NAI). He has published over 225 journal and refereed conference papers and holds 170 patents related to advanced device technologies.
Outside attendees need to contact Barry Schneider in order to obtain the site badges required to enter NIST grounds and to attend the seminar. 24 hour notice is required for US citizens and 3 days for non-US citizens. Please contact bis@nist.gov (link sends e-mail) to be added to the visitor list. Visitors must check in at the NIST Visitor Center to pick up their badges. A photo ID is required for US citizens and a passport or green card for foreign nationals. There is also the possibility of viewing the seminar as a webcast. Again, please contact Barry Schneider for details preferably by email.