Advanced Capacitance Metrology for Nanoelectronic Device Characterization

Published

October 5, 2009

Author(s)

Curt A. Richter, Joseph J. Kopanski, Yicheng Wang, Muhammad Y. Afridi, Xiaoxiao Zhu, D. E. Ioannou, Qiliang Li, Chong Jiang

Abstract

We designed and fabricated a test chip (consisting of an array of metal-oxide-semiconductor (MOS) capacitors and metal-insulator-metal (MIM) capacitors ranging from 0.3 fF to 1.2 pF) for use in evaluating the performance of new measurement approaches for small capacitances. The complete array of capacitances was measured to obtain a fingerprint of capacitance values. After correcting these data for pad and other stray capacitances, such data can be used to evaluate the relative accuracy and sensitivity of a capacitance measurement instrument or circuit. This test chip was used to assess the capabilities of two different capacitance measurement approaches: an LCR meter, and a capacitance bridge. A silicon-nanowire based capacitance test structure was fabricated and characterized by using the optimized capacitance measurement methods developed with the MOS/MIM test chip.

Proceedings Title

AIP Conference Proceedings, Frontiers of Characterization and Metrology for Nanoelectronics: 2009

Conference Dates

May 11-15, 2009

Conference Location

Albany, NY

Pub Type

Conferences

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Keywords

Nanoelectronics, test-structures, capacitance, nanowires, metal-insulator-semiconductor, metal-insulator-metal

Citation

Richter, C. , Kopanski, J. , Wang, Y. , Afridi, M. , Zhu, X. , Ioannou, D. , Li, Q. and Jiang, C. (2009), Advanced Capacitance Metrology for Nanoelectronic Device Characterization, AIP Conference Proceedings, Frontiers of Characterization and Metrology for Nanoelectronics: 2009, Albany, NY, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=903268 (Accessed October 30, 2025)