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You searched on: Author: richard allen Sorted by: date

Displaying records 1 to 10 of 126 records.
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Published: 5/2/2016
Authors: Richard A Allen, David Thomas Read, Victor H Vartanian, Winthrop A. Baylies, William Kerr, Mark Plemmons, Kevin T. Turner
Abstract: A round robin experiment to compare the sensitivities of various metrology tools to small voids between bonded wafers such as are used in three-dimensional stacked integrated circuits (3DS-ICs) and MEMS packaging. Participants received a set of f ...

2. Process Optimization for Lattice-Selective Wet Etching of Crystalline Silicon Structures
Published: 3/9/2016
Authors: Ronald G Dixson, William F Guthrie, Richard A Allen, Ndubuisi George Orji, Michael W. Cresswell, Christine E. Murabito
Abstract: Lattice-selective etching of silicon is used in a number of applications, but it is particularly valuable in those for which the lattice-defined sidewall angle can be beneficial to the functional goals. A relatively small but important niche applica ...

3. Metrology Needs for 2.5D/3D Interconnect
Published: 6/20/2014
Authors: Victor H Vartanian, Richard A Allen, Klaus Humler, Steve Olsen, Brian Sapp, Larry Smith
Abstract: This chapter will focus on the metrology steps to support 2.5D and 3D reference flows employing via-mid copper through-silicon via (TSV) processing, wafer thinning, and backside processing using a handle wafer and chip-to-chip bonding. Reference fl ...

4. Metrology for 3D Integration
Published: 5/13/2014
Authors: Richard A Allen, Victor H Vartanian, David Thomas Read, Winthrop A. Baylies
Abstract: Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through- silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patte ...

5. Metrology Needs for TSV Fabrication
Published: 3/4/2014
Authors: Victor H Vartanian, Richard A Allen, Larry Smith, Klaus Hummler, Steve Olson, Brian Sapp
Abstract: This paper focuses on the metrology needs and challenges of through silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper CMP. These TSVs, with typical dimensions within a f ...

6. Detection of 3D Interconnect Bonding Voids by IR Microscopy
Published: 2/20/2014
Authors: Jonny H?glund, Zoltan Kiss, Gyorgy Nadudvari , Zsolt Kovacs, Szabolcs Velkei, Moore Chris, Victor H Vartanian, Richard A Allen
Abstract: There are a number of factors driving 3D integration including reduced power consumption, RC delay, and form factor as well as increased bandwidth. However, before these advantages can be realized, various technical and cost hurdles must be overcom ...

7. TSV Reveal height and bump dimension metrology by the TSOM method
Published: 4/30/2013
Authors: Ravikiran Attota, Haesung Park, Victor H Vartanian, Ndubuisi George Orji, Richard A Allen
Abstract: Through-focus scanning optical microscopy (TSOM) transforms conventional optical microscopes into truly 3D metrology tools for nanoscale- to- microscale dimensional analysis with nanometer-scale sensitivity. Although not a resolution enhancement meth ...

8. The MEMS 5-in-1 Test Chips (Reference Materials 8096 and 8097)
Published: 3/27/2013
Authors: Janet M Cassard, Jon C Geist, Craig Dyer McGray, Richard A Allen, Muhammad Yaqub Afridi, Brian Joseph Nablo, Michael Gaitan, David G Seiler
Abstract: This paper presents an overview of the Microelectromechanical Systems (MEMS) 5-in-1 Reference Material (RM), which is a single test chip with test structures from which material and dimensional properties are obtained using five documentary standard ...

Published: 11/7/2012
Authors: Richard A Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David Thomas Read, Andreas Fehk¿hrer, J¿rgen Burggraf
Abstract: An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers thinned to 100 µm or less for three-dimensional stacked integrated circuits (3DS-ICs). 3DS-ICs hold the promise of improved pe ...

10. Robust Auto-Alignment Technique for Orientation-Dependent Etching of Nanostructures
Published: 5/29/2012
Authors: Craig Dyer McGray, Richard J Kasica, Ndubuisi George Orji, Ronald G Dixson, Michael W. Cresswell, Richard A Allen, Jon C Geist
Abstract: A robust technique is presented for auto-aligning nanostructures to slow-etching crystallographic planes in materials with diamond cubic structure. Lithographic mask patterns are modified from the intended dimensions of the nanostructures to compen ...

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