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1. Metrology Needs for 2.5D/3D Interconnect
Victor Vartanian, Richard A Allen, Klaus Humler, Steve Olsen, Brian Sapp, Larry Smith
This chapter will focus on the metrology steps to support 2.5D and 3D reference flows employing via-mid copper through-silicon
via (TSV) processing, wafer thinning, and backside processing using a handle wafer and chip-to-chip bonding. Reference fl ...
2. Metrology for 3D Integration
Richard A Allen, Victor Vartanian, David Thomas Read, Winthrop A. Baylies
Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-
silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patte ...
3. Metrology Needs for TSV Fabrication
Victor Vartanian, Richard A Allen, Larry Smith, Klaus Hummler, Steve Olson, Brian Sapp
This paper focuses on the metrology needs and challenges of through silicon via (TSV) fabrication, consisting of TSV etch, liner,
barrier, and seed (L/B/S) depositions, copper plating, and copper CMP. These TSVs, with typical dimensions within a f ...
4. Detection of 3D Interconnect Bonding Voids by IR Microscopy
Jonny H?glund, Zoltan Kiss, Gyorgy Nadudvari , Zsolt Kovacs, Szabolcs Velkei, Moore Chris, Victor Vartanian, Richard A Allen
There are a number of factors driving 3D integration including reduced power consumption, RC delay, and form factor as well as
increased bandwidth. However, before these advantages can be realized, various technical and cost hurdles must be overcom ...
5. TSV Reveal height and bump dimension metrology by the TSOM method
Ravikiran Attota, Haesung Park, Victor Vartanian, Ndubuisi George Orji, Richard A Allen
Through-focus scanning optical microscopy (TSOM) transforms conventional optical microscopes into truly 3D metrology tools for nanoscale- to- microscale dimensional analysis with nanometer-scale sensitivity. Although not a resolution enhancement meth ...
6. The MEMS 5-in-1 Test Chips
(Reference Materials 8096 and 8097)
Janet M Cassard, Jon C Geist, Craig Dyer McGray, Richard A Allen, Muhammad Yaqub Afridi, Brian Joseph Nablo, Michael Gaitan, David G Seiler
This paper presents an overview of the Microelectromechanical Systems (MEMS) 5-in-1 Reference Material (RM), which is a single test chip with test structures from which material and dimensional properties are obtained using five documentary standard ...
7. EVALUATING METHODS OF SHIPPING THIN SILICON WAFERS FOR 3D STACKED APPLICATIONS
Richard A Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David Thomas Read, Andreas Fehk¿hrer, J¿rgen Burggraf
An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers
thinned to 100 µm or less for three-dimensional stacked integrated circuits (3DS-ICs). 3DS-ICs hold the promise of improved
8. Robust Auto-Alignment Technique for Orientation-Dependent Etching of Nanostructures
Craig Dyer McGray, Richard J Kasica, Ndubuisi George Orji, Ronald G Dixson, Michael W Cresswell, Richard A Allen, Jon C Geist
A robust technique is presented for auto-aligning nanostructures to slow-etching crystallographic planes in materials with diamond
cubic structure. Lithographic mask patterns are modified from the intended dimensions of the nanostructures to compen ...
9. Rectangular Scale-Similar Etch Pits in Monocrystalline Diamond
Craig Dyer McGray, Richard A Allen, Marc J Cangemi, Jon C Geist
Etching of monocrystalline diamond in oxygen and water vapor at 1100° C through small pores in a silicon nitride film produced smooth-walled rectangular cavities. The cavities were imaged by electron microscope and measured by interferometric microsc ...
10. Test Structure Fundamentals
Richard A Allen
Test structures are critical tools for semiconductor manufacturers, allowing for understanding of the process and individual circuit
elements that cannot be acquired from measurements of the circuits, which can have billions of transistors and othe ...