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Back-End-of-Line Reliability Metrology Development

Summary:

The Back-End-of-Line (BEOL) Reliability Metrology Development project aims to develop the metrology to enable quantitative and mechanistic assessment of performance limiting reliability issues in emerging electronic devices related to new materials, processes, and integration schemes.

Description:

The Back-End-of-Line Reliability Metrology Development project supports the PML priorities in Measurements for Advanced Manufacturing in the areas of Nano-manufacturing, Novel devices, and Electronic materials. Specifically, the project aims to develop the metrology to enable the quantitative and mechanistic assessment of performance limiting reliability issues in emerging electronic devices related to new materials, processes, and integration schemes. Examples include metrology and documentary standards to enable 3D integration of integrated circuits.

The ultimate aim of the project is to develop the metrology to enable fundamental Physics of Failure (PoF) approach to reliability assessments in support of designed-in reliability in nano-manufacturing of advanced electronics. Our work uses direct experimental measurements, inferred root causes of failure such as thermo-mechanical stress, fatigue, fracture, wear, and corrosion, to inform modeling and simulation to address various failure mechanisms in electronic devices. In this work, it helps to understand material choices and integration, and their impact of on system performance.

The project leverages competencies in scanning probe based metrology, electromagnetics (broadband RF-measurements), X-ray micro-diffraction, material mechanics and semiconductor process integration knowledge to achieve its’ goals. We work collaboratively with national and international partners, such as SEMATECH, iNEMI, HDPUG, SEMI and CEA-Leti.

Major Accomplishments:

  • Demonstrated the ability of scanning probes to characterize buried interfaces in the context of BEOL Reliability
  • Demonstrated the use of broadband high frequency electromagnetic wave (RF) methods to non-destructively identify, classify, and characterize performance-limiting defects in emerging nanoelectronic devices
  • Achieved depth dependent measurement of the full strain/stress tensors in copper through-silicon via (TSV) using synchrotron-based X-ray microbeam diffraction technique
  • Continue to develop RF spectroscopy techniques to monitor / study BEOL devices
Press:

Stressing Out Copper TSVs with Temperature

Lead Organizational Unit:

pml

Staff:

Yaw Obeng, Project Leader
Joseph Kopanski


Thermal Cycling System

NIST-built Thermal Cycling System.

 

Schematic diagram of a 3D stacked integrated circuit (3D-SIC), achieved using copper through-silicon via (TSV) interconnects

Schematic diagram of a 3D stacked integrated circuit (3D-SIC), achieved using copper through-silicon via (TSV) interconnects.


SEM cross-sectional image of the two-level 3D stacked integrated circuit used for our studies

SEM cross-sectional image of the two-level 3D stacked integrated circuit used for our studies.

Contact

Yaw Obeng
301-975-8093

100 Bureau Drive, M/S 8120
Gaithersburg, MD 20899-8120