Device-Level PBTI-induced Timing Jitter Increase in Circuit-Speed Random Logic Operation

Published

July 31, 2014

Author(s)

Jiwu Lu, Canute I. Vaz, Jason P. Campbell, Jason T. Ryan, Kin P. Cheung, Guangfan Jiao, Gennadi Bersuker, Chadwin D. Young

Abstract

We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar increases in random timing jitter. This calls into question the widely assumed degradation headroom between DC and AC measurements. This work collectively provides a snapshot of PBTI degradation in “real” circuit environments. It provides a path for more accurate and realistic circuit lifetime estimations and circuit timing budget criteria.

Proceedings Title

IEEE Symposia on VLSI Technology and Circuits

Conference Dates

June 9-13, 2014

Conference Location

Honolulu, HI

Pub Type

Conferences

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Keywords

Positive Bias Temperature Bias (PBTI), Pseudo-Random Binary Sequency (PRBS), Eye diagram, Jitter

Citation

Lu, J. , Vaz, C. , Campbell, J. , Ryan, J. , Cheung, K. , Jiao, G. , Bersuker, G. and D., C. (2014), Device-Level PBTI-induced Timing Jitter Increase in Circuit-Speed Random Logic Operation, IEEE Symposia on VLSI Technology and Circuits, Honolulu, HI, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=915922 (Accessed April 26, 2024)