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|Author(s):||Yaw S. Obeng; Chukwudi A. Okoro; Joseph J. Kopanski;|
|Title:||Metrology for Nanosystems and Nanoelectronics Reliability Assessments|
|Published:||August 20, 2012|
|Abstract:||The traditional models and techniques for studying reliability in integrated circuits may not be appropriate for nanoelectronics and nanosystems. In this paper, we present an overview of a number of materials and metrology techniques currently under development in our group at NIST. Among other topics, we will assess the techniques and models currently used for evaluating integrated circuit reliability, as well as present some new approaches.|
|Conference:||12th IEEE NanoTechnology Conference,|
|Dates:||August 20-23, 2012|
|Keywords:||CBCM, charge based capacitance measurement, interconnects, metrology techniques, nanoelectronics, reliability, three-dimensional integrated circuits, through silicon vias, TSVs|
|PDF version:||Click here to retrieve PDF version of paper (750KB)|