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|Author(s):||Xiaoxiao Zhu; Qiliang Li; D. E. Ioannou; Diefeng Gu; John E. Bonevich; Helmut Baumgart; John S. Suehle; Curt A. Richter;|
|Title:||Fabrication, Characterization and Simulation of High Performance Si Nanowire-based Non-Volatile Memory Cells|
|Published:||May 16, 2011|
|Abstract:||We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO2 charge trapping layers of varying thickness. The memory cells, which are fabricated by self-aligning in-situ grown Si nanowires, exhibit high performance, i.e., fast Program/Erase operations, long retention time, and good endurance. The effect of trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO2 increases from 5 nm to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. This data indicates that the electric field across the tunneling oxide is not affected by HfO2 thickness, which is in a good agreement with simulation results. Our work also shows that the Ω-gate structure improves the program speed and retention time for memory application.|
|Keywords:||non-volatile memory, Si nanowire, nanoelectronics, charge trapping|
|Research Areas:||Nanoelectronics and Nanoscale Electronics|
|PDF version:||Click here to retrieve PDF version of paper (1MB)|