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|Author(s):||Michael W. Cresswell; Robert Allen; L Linholm; William F. Guthrie; William B. Penzes; A Gurnell;|
|Title:||Hybrid Optical-Electrical Overlay Test Structure|
|Published:||January 01, 1997|
|Abstract:||This paper describes the exploratory use of electrical test structures to enable the calibration of optical overlay instruments of the type used to monitor semiconductor-device fabrication processes. Such optical instruments are known to be vulnerable to hard-to-determine systematic process- and instrument-specific errors known as shifts. However, these shift errors generally do not affect electrical test-structure measurements extracted from the same features. Thus the opportunity exists to configure physical standards having overlay targets that can be certified by electrical means, thereby enabling estimates of the shifts prevailing in a particular application. In this work, a new hybrid test structure, meaning one from which overlay measurements can be extracted electrically, as well as by optical instruments, has been designed and fabricated with built-in overlay values ranging from -60 to +60 nm. A selection of structures constituting a test chip has been patterned in a single conducting film with CD (critical dimension) design rules ranging from 1.0 um to 2.0 um and fabricated and tested. Electrical overlay parameters, derived from multiple step-and-repeat die-site measurements, generally match the corresponding optical measurements to within several nanometers, subject to limitations of the pattern-replication process. This paper focuses on the extraction of overlay from the electrical measurements, the dependence of the measurements on CD design rules, and their comparison with the corresponding measurements made both by a commercial optical-overlay instrument and by a coordinate-measurement system having measurements traceable to absolute dimensional standards. It is presented as a first step toward the use of electrical measurements for advancing shift management in optical overlay of features patterned in separate lithographic processes.|
|Citation:||IEEE Transactions on Semiconductor Manufacturing|
|Pages:||pp. 250 - 255|
|Research Areas:||Metrology, Manufacturing|