NIST logo

Publication Citation: The Challenge of Measuring Defects in Nanoscale Dielectrics

NIST Authors in Bold

Author(s): Kin P. Cheung; John S. Suehle;
Title: The Challenge of Measuring Defects in Nanoscale Dielectrics
Published: May 26, 2008
Abstract: Defects in nanoscale gate dielectric of MOS devices can exchange charges with the substrate via quantum mechanical tunneling. This characteristic has been utilized in many measurement methods to measure the defects and its spatial distribution. In some cases, the quantitative relationship between tunneling time and defect depth can be established. In other cases, this is not yet possible due to the lack of knowledge about the interface trap-fill time. As gate dielectrics reaches less than 1 nm equivalent oxide thickness, the measurement techniques must be made at higher speeds. Measurement into the GHz range will be needed.  
Conference: 213th Meeting of the Electrochemical Society
Proceedings: 213th ECS meeting: Dielectrics for Nanosystems
Pages: pp. 123 - 128
Location: Phoenix, AZ
Dates: May 19-22, 2008
Keywords: CMOS; defect; gate dielectric; nano; trap-fill time; charge-pumping; noise
Research Areas: Nanoelectronics and Nanoscale Electronics