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You searched on: Author: john suehle

Displaying records 31 to 40 of 180 records.
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31. Wafer-level Hall Measurement on SiC MOSFET
Published: 10/16/2009
Authors: Liangchun (Liangchun) Yu, Kin P Cheung, Vinayak Tilak, Greg Dunne, Kevin Matocha, Jason P Campbell, John S Suehle, Kuang Sheng
Abstract: Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements over ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=907098

32. Gate Oxide Long-Term Reliability of 4H-SiC MOS Devices
Published: 10/14/2009
Authors: Liangchun (Liangchun) Yu, Kin P Cheung, Greg Dunne, Kevin Matocha, John S Suehle, Kuang Sheng
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=907099

33. Wafer-level Hall Measurement on SiC MOSFET
Published: 10/11/2009
Authors: Liangchun (Liangchun) Yu, Kin P Cheung, Vinayak Tilak, Greg Dunne, Kevin Matocha, Jason P Campbell, John S Suehle, Kuang Sheng
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=905438

34. Application of ALD High-k Dielectric Films as Charge Storage Layer and Blocking Oxide in Nonvolatile Memories
Published: 10/6/2009
Authors: Xiaoxiao Zhu, H Gu, Qiliang Li, Helmut Baumgart, D. E Ioannou, John S Suehle, Curt A Richter
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=907139

35. Silicon Nanowire NVM with High-k Gate Dielectric Stack
Published: 9/1/2009
Authors: Xiaoxiao Zhu, D. Gu, Qiliang Li, D. Ioannoua, H. Baumgart, John S Suehle, Curt A Richter
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=904090

36. Steep Subthreshold Slope Nanowire FETs with Gate-Induced Schottky-Barrier Tunneling
Published: 6/24/2009
Authors: Qiliang Li, Xiaoxiao Zhu, D. Ioannou, John S Suehle, Curt A Richter
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=904092

37. Flexible Solution-Processed Memristors
Published: 6/3/2009
Authors: Nadine Emily Gergel-Hackett, Behrang H Hamadani, B Dunlap, John S Suehle, Curt A Richter, Christina Ann Hacker, David J Gundlach
Abstract: We have fabricated physically flexible nonvolatile memory devices using inexpensive, room-temperature, solution processing. The behavior of these devices is consistent with that of a memristor device, the missing fourth circuit element theoreticall ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=900874

38. Large Random Telegraph Noise in Sub-Threshold Operation of Nano-Scale nMOSFETs
Published: 5/18/2009
Authors: Jason P Campbell, Liangchun (Liangchun) Yu, Kin P Cheung, Jin Qin, John S Suehle, A Oates, Kuang Sheng
Abstract: We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-VTH) operation of highly scaled devices. We find that the sub-VTH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by c ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=902184

39. The Negative Bias Temperature Instability vs. High-Field Stress Paradigm
Published: 5/18/2009
Authors: Jason P Campbell, Kin P Cheung, John S Suehle, A Oates
Abstract: A new and more accurate fast-IDVG measurement methodology is utilized to examine the transient degradation and recovery associated with the negative-bias temperature instability (NBTI). The results reveal that the anomalously large initial degradatio ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=902213

40. Random Telegraph Noise in Highly Scaled nMOSFETs
Published: 4/26/2009
Authors: Jason P Campbell, Jin Qin, Kin P Cheung, Liangchun (Liangchun) Yu, John S Suehle, A Oates, Kuang Sheng
Abstract: Recently 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversio ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=901584



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