| Author(s): |
Joan Boyar; Rene C. Peralta; |
| Title: |
A depth-16 circuit for the AES S-box |
| Published: |
December 01, 2011 |
| Abstract: |
New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-box and its inverse, consisting of 63 gates. |
| Citation: |
IACR Cryptology ePrint Archive |
| Website: |
http://eprint.iacr.org/2011/332 |
| Volume: |
2011 |
| Pages: |
11 pp. |
| Keywords: |
AES; S-box; finite field inversion; circuit complexity; circuit depth. |
| Research Areas: |
Computer Security, Cybersecurity |
| PDF version: |
 Click here to retrieve PDF version of paper (545KB) |
