Thermally induced warpage of printed wiring boards (PWB) and printed circuit assemblies (PCA) is an increasingly important issue in managing the manufacturing yield and reliability of electronic devices. In this paper, we introduce complementary simulation and experimental verification procedures capable of investigating warpage at the local feature level as well as the global PCB level. Simulation within a standards-based engineering framework allows efficient introduction of detailed feature information into the warpage model. Experimental results derived from temperature-dependent shadow moir¿ provide a rapid high resolution picture of local warpage in critical regions. We describe these results for two unpopulated PWB test cases.
Proceedings Title: 5th International Conference on Thermal, Mechanical and Thermo-mechanical Simulation and Experiments in Micro-electronics and Micro-systems
Conference Dates: May 11-13, 2004
Conference Location: Brussels, BE
Conference Title: EuroSimE 2004
Pub Type: Conferences
Analysis, AP210, Framework, Multi-Representation Architecture, Phase Stepping, Shadow Moire, Standards, STEP, Warpage