This paper focuses on the metrology needs and challenges of through silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper CMP. These TSVs, with typical dimensions within a factor of two or so of ~5 micrometers x 50 micrometers (diameter x depth) present a new set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of liner, barrier metal, and seed metal; metrology for these layers ensures that there is complete coverage of the sidewalls, providing electrical isolation from the wafer. Metrology for the fill step includes verifying that the TSVs are deposited without voids, and that the extent of stress on the surrounding silicon does not exceed acceptable limits.
Citation: Journal of Micro/Nanolithography, MEMS, and MOEMS
Pub Type: Journals
through silicon via (TSV), three dimensional stacked integrated circuits (3D-IC, 3DS-IC), metrology