The traditional models and techniques for studying reliability in integrated circuits may not be appropriate for nanoelectronics and nanosystems. In this paper, we present an overview of a number of materials and metrology techniques currently under development in our group at NIST. Among other topics, we will assess the techniques and models currently used for evaluating integrated circuit reliability, as well as present some new approaches.
Proceedings Title: TBD
Conference Dates: August 20-23, 2012
Conference Location: Birmingham, -1
Conference Title: 12th IEEE NanoTechnology Conference,
Pub Type: Conferences
CBCM, charge based capacitance measurement, interconnects, metrology techniques, nanoelectronics, reliability, three-dimensional integrated circuits, through silicon vias, TSVs