We developed an electrical test to evaluate interconnections in packaged, electrostatic-discharge (ESD) protected modules. The ESD protection circuit, which in modern integrated circuits is present at every I/O as an inherent part of the chip structure, can be employed to create an electrical path through the interconnection without powering ON the internal circuitry of the chip. The technique utilizes a chip-specific voltage-current characteristic, and a model of the interconnection, from which the interconnection ohmic resistance can be directly obtained. The technique is applicable to a broad range of functional packages. Its sensitivity is comparable or better than the sensitivity of standard test techniques that utilize specialized test chips. This technique can also be used to test interconnections in failed IC s, since integrity of the internal circuitry is not required in this test.
Proceedings Title: AIP Conference Proceedings, Characterization and Metrology for ULSI Technology, vol 449, pp607-609 (1998)
Conference Dates: March 3, 1998
Conference Location: Gaithersburg, MD
Conference Title: Characterization and Metrology for ULSI Technology, 1998 International Conference
Pub Type: Conferences
chip carriers, electrostatic discharge protection, interconnection resistance, nonlinear resistance, statistical data analysis