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Mark D. Stiles (Fed)

Mark Stiles is a Project Leader and NIST Fellow in the Alternative Computing Group in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML). His research, published in over 165 papers, has focused on the development of a variety of theoretical methods for predicting the properties of magnetic nanostructures and has recently shifted to neuromorphic computing. He has helped organize numerous conferences and has served the American Physical Society on the Executive Committee of the Division of Condensed Matter Physics and as Chair and on the Executive Committee of the Topical Group on Magnetism. He has also served as a Divisional Associate Editor for Physical Review Letters, served on the Editorial Board of Physical Review Applied, and is an Associate Editor for Reviews of Modern physics. Mark is a Fellow of the American Physical Society and IEEE and has been awarded the Silver Medal from the Department of Commerce and the Samuel Wesley Stratton Award from NIST.

Projects

Selected Publications

Publications

Measurement-driven Langevin modeling of superparamagnetic tunnel junctions

Author(s)
Liam Pocher, Temitayo Adeyeye, Sidra Gibeault, Philippe Talatchian, Ursula Ebels, Daniel Lathrop, Jabez J. McClelland, Mark Stiles, Advait Madhavan, Matthew Daniels
Superparamagnetic tunnel junctions are important devices for a range of emerging technologies, but most existing compact models capture only their mean

Neural networks three ways: unlocking novel computing schemes using magnetic tunnel junction stochasticity

Author(s)
Matthew Daniels, William Borders, Nitin Prasad, Advait Madhavan, Sidra Gibeault, Temitayo Adeyeye, Liam Pocher, Lei Wan, Michael Tran, Jordan Katine, Daniel Lathrop, Brian Hoskins, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Due to their interesting physical properties, myriad operational regimes, small size, and industrial fabrication maturity, magnetic tunnel junctions are

Patents (2018-Present)

Quasi-Systolic Processor and Quasi-Systolic Array

NIST Inventors
Brian Hoskins , Matthew Daniels , Mark D. Stiles and Advait Madhavan
A quasi-systolic array includes: a primary quasi-systolic processor; an edge row bank and edge column bank of edge quasi-systolic processors; and an interior bank of interior quasi-systolic processors. The primary quasi-systolic processor, edge quasi-systolic processor, and interior quasi-systolic

Timing-Based Computer Architecture Systems And Methods

NIST Inventors
Advait Madhavan , Mark D. Stiles and Matthew Daniels
Tropical algebra is an emerging field of mathematics concerned with graph theory, control theory, and certain optimization problems, especially in discrete event systems. We developed a novel computer circuit called a tropical state machine that uses signal timing and the physics of nanodevices to
Created October 9, 2019, Updated August 22, 2023