Innovations in Semiconductor Devices for Exascale Computing
IBM Fellow and Vice President of Science and Technology
IBM Watson Research Center
Friday, Oct. 30, 2009
10:30 a.m., Green Auditorium
Images provided by the speaker
The continuous scaling of CMOS device technology has enabled system performance to double every two years for the past 40 years. However, emerging classes of applications for which network-speed processing and data-intensive modeling are integral components will demand a much faster rate of improvement, such as 2x/year in order to reach exaflop capabilities (100x-1000x over present systems) by the end of the next decade. These applications require continued innovation to increase intrinsic transistor performance power and density. New system architectures will take advantage of 3D chip technology to enable a higher level of hybrid integration, new memory technology such as Phase Change Memory (PCM) will allow implementation of a new level of memory architecture, and silicon photonics on the processor will meet ultra-low power, low cost and high density communications needs. These and other innovations will lead to significant improvement in systems integration, performance, and power efficiency.
Anyone outside NIST wishing to attend must be sponsored by a NIST employee and receive a visitor badge. For more information, call Kum J. Ham at 301-975-4203.
Colloquia are videotaped and available in the NIST Research Library.