Accurate prediction, validation and reduction of thermally-induced PCB warpage are critical for enhancing manufacturing yield and reliability in time-to-market driven electronics product realization. In this paper, we describe a methodology to simulate thermally-induced warpage of PCBs and PCAs. We will demonstrate this analysis methodology using the following path: read ECAD designs from Mentor Board Station, identify features relevant to warpage analysis, create idealized analysis models, select solution technique and create solver-specific models (e.g. ANSYS models for finite-element solution), identify warpage-hotspots and calculate metrics to assist PCB/A designers in reducing warpage. We shall also present initial results from experimental verification of this technique using Shadow Moire (TherMoire) method. This methodology reuses analysis concepts, idealizations, and solution techniques for modularized and configurable simulation studies. It uses ISO 10303 technologies (STEP AP210 - www.ap210.org and Standard Data Access Interface - see www.jsdai.net).
Proceedings Title: Proceedings of the Mentor Graphics International User2User Conference
Conference Dates: May 2-5, 2006
Conference Location: San Jose, CA
Conference Title: 2006 Mentor Graphics International User2User
Pub Type: Conferences
AP210, Modeling, STEP, Warpage