This paper presents the results from a parametric simulation study that was conducted to optimize the performance of 100 A, 10 kV, 20 kHz half-bridge SiC MOSFET/JBS power modules. The power modules are being developed by the DARPA WBGS-HPE Phase II program and will be used in construction of the 13.8 kV, 2.75 MVA SSPS developed in the Phase III program. The simulations are performed using recently developed and validated physics-based electrical and thermal models. The total device active areas and the various gate resistances and inductances are optimized in order to minimize overall power dissipation. A detailed description of the loss mechanisms and the simulation results for a representative SSPS topology is also presented.
Proceedings Title: Proc., Power Electronics Specialist Conference
Conference Dates: June 15-19, 2008
Conference Location: Rhodes, GR
Conference Title: Power Electronics Specialist Conference
Pub Type: Conferences
Silicon carbide, high-voltage, high-frequency, MOSFET, Junction Barrier Schottky (JBS), half-bridge power module, Solid State Power Substation.