In-line, non-destructive process control metrology of high aspect ratio (HAR) holes and trenches has long been a known gap in metrology. Imaging the bottoms of at-node size beyond 10:1 AR contact holes in oxide has not yet been demonstrated. Nevertheless, holes and trenches of 30:1, 40:1, or even 60:1 will soon enter production, with these etches being applied to various homogeneous and multi-layer stacks of Si and SiO2. The need comes from Moores Law and increasing functional density on microchips, for which true 3D memory devices will soon be manufactured. These can take many different forms, but a common building block will be these ultra-HAR etched features. In this work, we show experimental and simulated results from the NIST JMONSEL program to assess the feasibility of measuring such features using both conventional low voltage scanning electron microscopy (SEM) and higher beam energies and low vacuum conditions to ameliorate charging. In our measurements, higher voltage SEM did not improve upon conventional critical dimension (CD)-SEM. Simulations suggest the reason is a failure to overcome a negative surface potential. Although a signal can be detected from the bottom of contact holes in typical imaging conditions, in the CD-SEM, it is likely that it will be very small and possibly below the noise floor.
Proceedings Title: Metrology, Inspection, and Process Control for Microlithography XXVI, Proceedings of SPIE Volume: 8324
Conference Dates: February 12-16, 2012
Conference Location: San Jose, CA
Pub Type: Conferences
CD-Metrology, 3D Memory, CD-SEM, contact holes, HAR features