Given the recent shortages of liquid helium, cryogen-free operation of superconducting devices such as programmable Josephson voltage standard (PJVS) systems has become preferred worldwide, and a necessity in some locations. Besides consistent and accurate operation of these devices on a cryocooler, minimization of the impact of the cryocooler system on the laboratory environment is also important, with the ideal field-deployable system employing an air-cooled compressor with 110 V input and minimum heat rejection to the environment. The cooling capacity of cryocooler systems meeting these criteria is quite limited however (nominally 100 mW capacity at 4.2 K) and using such a system to provide metrology-grade, precision voltage standards imposes a stringent set of design constraints. In this work we have systematically investigated the performance of NIST 10 V PJVS chips employing Nb/NbxSi1-x/Nb superconducting junctions as a function of temperature, and have addressed the major factor limiting the performance of a cryocooled PJVS: the thermal gradients between the chip and the cryocooler. Through the development of a robust and reproducible method for soldering chips to a Cu carrier (package) we have increased the thermal conductances within the packaging to their effective maximum values. The results show that while the cryogen-free operation of a current generation NIST 10 V PJVS is not possible on a 100 mW cryocooler, it is possible to confidently predict the cooling power required for cryogen-free operation of a NIST 10 V PJVS.
Citation: Applied Superconductivity
Pub Type: Journals
Josephson arrays, Primary standards, Superconducting device packaging, Voltage, Thermal conductance