You, L.
, Ahn, J.
and Kopanski, J.
(2014),
DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY, 2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics, Gaithersburg, MD, US
(Accessed April 19, 2024)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY
Published
Author(s)
, ,
Proceedings Title
2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics
Conference Dates
March 25-28, 2013
Conference Location
Gaithersburg, MD, US
Pub Type
Conferences
Citation
Created March 24, 2014, Updated October 12, 2021