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The NIST Mark-III Microphone array

Photo of the complete microphone array
                                    version 1. Obsolete version (v1) of the Mk-III Microphone Array.
Photo of the complete microphone
                                      array version 2. Current version (v2) of the Mk-III Microphone Array.

Research Goals

In order to support our continuing research initiative in spoken language systems we make data acquisition and measurement tools available to industry to facilitate their product research and development. Accordingly, the technical objective of this third generation microphone array reference platform is to allow interested laboratories access to a relatively cheap and reliable means of acquiring multi channel speech signals suitable for phased array processing research. The Mark-III array is designed to minimize analog signal paths to reduce noise, and also allow flexible deployment in research laboratories.

To reduce the complexity of the design, and make it modular, it was decided to separate the functions on two different types boards. First, the Microboard, which is a sound capture device performing eight channels of digitization and offering a serial data stream, and second a Motherboard which captures and formats data from the eight Microboards and sends the resulting sixty four channels as a UDP packet stream via Ethernet a Data Flow Client for processing. This architecture is shown at a high level below:

General Schematic of the microphone
                                       array.

Detailed design information about the microphone array is available from the download section below. The support software we developed in order to develop and debug the array platform, and to actually operate it is also available.


The Hardware

Photo of the Microboard Version 1.     Photo of the Motherboard.
Photo of the Microboard Version 1     Photo of the Motherboard
Photo of the Microboard Version 2.     Photo of the Powerboard for
                                    the version 2.
Photo of the Microboard Version 2     Photo of the Powerboard for the version 2
Photo of the back of the
                                    Motherboard.     
Photo of the back of the Motherboard     

The Microboard performs three stages of processing:

  • Microphone amplification to line level
  • Analog to digital conversion,
  • Serial connection to the motherboard

The Motherboard is connected to 8 of these Microboards via cables, and has an FPGA as its main processor. It also has support logic to provide:

  • 4 MBytes of SRAM for buffering and retransmitting of data
  • Fast Ethernet physical layer device (PHY)
  • DIP switch to configure the MAC address
  • A clock synchronization signal connection to other possible microphone arrays
  • PROM to contain firmware that is loaded at power up
  • Condition indicator LEDs.

More information about the microphone array is available from the download section.

Installation Steps of version 2

Step 01. Picture
                                    showing how to connect the Microboard to the
                                    Motherboard with the data cable. This step
                                    needs to be done for each of the 8
                                    Microboards.     Step 02. Picture showing
                                    how to connect the Microboard to the
                                    Powerboard. This step needs to be done for
                                    each of the 8 Microboards.
Step 01 (8 times)     Step 02 (8 times)
Step 03.
                                    Picture showing how to connect the Volt
                                    meter on the Powerboard.     Step
                                    04. Picture showing how to connect the
                                    ON/OFF switch to the Powerboard
Step 03     Step 04
Step 05. Picture showing
                                    how to connect the ground cable to the
                                    motherboard when using a metal box.     Step 06. Picture showing
                                    how to plug the power cable and the ethernet
                                    cable on the motherboard.
Step 05     Step 06

The step 01 and 02 have to be repeated 8 times for each board. BE CAREFUL there is an order to put the cards ( cf user manual). The whole system should be tested with the digital oscilloscope provided below.

Installation of version 1 require only the steps 01, 05 and 06.

The VHDL program for the FPGA

Gathering Schematic of the
                                    main modules.

The program for the FPGA firmware is composed of several VHDL modules that are interconnected, each module with a particular task as follows:

  • data capture
  • SRAM interface with the FPGA
  • create UDP frames from captured sound data,
  • create a BOOTP request frame
  • create an ARP response frame
  • create a response on status UDP frame
  • multiplexing
  • a 8 bit CRC32 computation
  • create transmission frames
  • store incoming messages
  • understand incoming messages
The main module coordinates these modules, running the system as a whole.

If you want more information about the VHDL module structure, Download the documentation file.


FAQ

  • Do I have the latest PROM version?

To know that, you have to start the digital oscilloscope and see the information at the top. it shoould be written something like: "Microphone Array ID: 300 with PROM CMA3v920". The value that you are looking for is CMA3v920. For any value like CMA3v918, you on't have the latest prom

  • What is the default voltage of the Motherboard?

The default voltage is 9V.


Acknowledgment of Contributors to the NIST Microphone Array Series

The development of a complex hardware/software system that challenges the prevailing state of the art in data throughput, signal processing, parallel distributed processing and networked sensor architecture is always the work of many individuals and organizations. The U. S. National Institute of Standards and Technology Information Technology Laboratory worked extensively with the Rutgers CAIP Center in the early years of the project to develop the first and second generation microphone arrays. More recently we have worked with many excellent investigators and software engineers of the EU Computer Human in the Loop (CHIL) project, of the OHSI multimodal research laboratory, and IBM Research, and several others. With apologies to anyone we have inadvertently left out, individuals who have made significant contributions over the years have included:

  • Dr. Martin Herman, Chief of Information Access Division - Supported the project in his Division and provided much useful input on the overall Smart Space testbed architecture over a period of years.
  • Mr. Vince Stanford, NIST Smart Space Project Manager - Managed the data flow and array projects for the Mk-I, Mk-II, and Mk-III array generations. He also provided conceptual guidance on the data flow system architecture based on his work in this area in the 1980s. He fabricated the Mk-I generation prototypes, and developed test software, beamforming algorithms including linearly constrained LMS adaptive systems, and developed prototypes of user sensitive, interfaces using speech acquired via microphone arrays. Debugged hardware and software performance issues, and brought teams together to solve the numerous technical issues.
  • Dr. James Flanagan, Director of the Rutgers CAIP Center - Dr. Jim graciously provided generous conceptual guidance and made his existing prototype arrays available to us for analysis. He also opened his laboratories and staff to us while we learned about the technology.
  • Dr. Gary Elko - Developer of the original prototypes that Dr. Flanagan kindly provided. Recently has offered technical inputs and professional judgment of ideas.
  • Mr. Joe French - Lab technical leader who tirelessly provided lengthy and detailed analyses of the hardware fabrication techniques, and used in previous the Mk-I, and Mk-II generations of hardware.
  • Ms. Christelle Martin - Developed array design software in Mathematica that provides frequency wave number plots that supported the design process. Also developed IDEF0 design documentation for the initial Smart Space deployment of the Mk-II arrays.
  • Mr. Fabrice Mougin - Developed the microphone amplification circuits and test suites for the Mk-II generation array and built the initial Mk-II prototypes and brought them to full functionality.
  • Mr. Olivier Galibert - Developed Linux driver software for the Mk-II generation data acquisition and source bearing estimation software. He developed the basic data flow architecture used to run all of the DSP pipelines and the array data acquisition system. He also provided detailed consultations on the systems and networking aspects of the Mk-III generation hardware and software.
  • Mr. Cedrick Rochet - Worked tirelessly to define and design the Mk-III generation to correct many of the difficulties of the Mk-II generation. He did board layouts, physical prototypes, VHDL programming, produced many test and evaluation software components, developed a reference specification and supervised the initial production runs by board fabrication houses. He wrote significant documentation and and supported numerous deployments at other laboratories. He also fabricated multiple copies of the Mk-II generation for early data collection experiments.
  • Dr. Maurizio Omologo - Maurizio and his colleagues have developed noise reduction techniques to significantly improve the SNR of the Mk-III generation arrays and graciously offered them for the Mod 1 version of the Mk-III reference design.
  • Roger Xu - He and his team at Intelligent Automation Incorporated who conducted analyses of phase and noise issues from power supplies that verified and extended results discovered by Omologo et al. His group also showed feasibility of the user sensitive interface by performing speaker identification and speech recognition using the Mk-III array and data flow system.
  • Dr. John McDonough - He and his group deployed and improved the NIST data flow, and developed methods to study its usefulness in source location, and for speech recognition at a distance. His team also developed Python bindings and debugged the data flow system that operates the Mk-III array.

Created on 2008-06-18 by Antoine Fillinger - Last updated on 2008-11-23 by Antoine Fillinger