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Subsections

• 2.2.1 An overview
• 2.2.2 Power stage
• 2.2.3 PROM stage
• 2.2.4 Clock stage
• 2.2.5 Data collection stage
• 2.2.6 FPGA stage
• 2.2.7 Memory stage
• 2.2.8 Ethernet stage

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2.2 Motherboard

2.2.1 An overview

As you can see on the figure , the FPGA is the gathering part of the project.

The cables at the top of the figure  are the data collection cables connected to the 8 microboards.

The red DIP is here to fix the MAC address of the microphone array.

The LEDs are here to give the status of the microphone array but we will see that deeper later.

From the figure  we can divide this board into seven parts:

• the power stage ( 2.5V, 3V, 5V),
• the PROM stage,
• the clock stage ( 25MHz and 33.8688MHz),
• the data collection stage,
• the FPGA stage,
• the memory stage,
• the ethernet stage ( 80225, H1089 and RJ45),

This board like the microboard is done in 4 layers to reduce it's size and have a better signal integrity.

2.2.2 Power stage

At the level of the power supply, I didn't use the 110V as main power supply because the project is open-source and safety considerations are important. So if our users make the same one, the DC 9V from an external transformer will be safer. The Toshiba memory used and the 2 oscillators require a voltage of 5V.

But the FPGA needs 2.5V and 3.3V(I/Os). So after some research, I found the Burr-Brown's REG104. The REG104 is a family of low-noise, low-dropout linear regulators with low ground pin current. The specification was better than everything else so I used it in 3 different versions for the 3 different voltages presented in the figure: . You can find its specification here: http://www-s.ti.com/sc/psheets/sbvs025b/sbvs025b.pdf.

2.2.3 PROM stage

In order to have an automatic programming of the FPGA at startup, I had a PROM in which the VHDL program is burned. We will see later about this program.

As told in the documentation of the FPGA, the PROM chosen was the XC17S200 because of its memory size of 2Megs. You can find its specification here: http://www.xilinx.com/bvdocs/publications/ds078.pdf.

2.2.4 Clock stage

This stage is used two times in the design as presented in figure :

• to give the main clock for the digitalization to the FPGA which creates three clocks form it ( LRCK, BCK, SCKI),
• to give the 25MHz clock to the ethernet as we will see later.

The RLC system is here to clean the bounce created by the oscillator.

2.2.5 Data collection stage

On the motherboard there is 8 connectors and the clocks signals created by the FPGA are amplified 8 times for the 8 microboards (cf figure: ).

The data lines are directly connected to the I/O pins of the FPGA.

The output of the FPGA is not appropriate to drive the clocks of 32 converters, so I used two clock drivers with a low-skew propagation delay: the CDCV304. You can find its specification here: http://www-s.ti.com/sc/ds/cdcv304.pdf.

The six CDCV304 are decoupled with six capacitors.

As previously the 100 resistors are for the signal integrity of the clocks because of the transmission line between the PCM1802 and the FPGA.

2.2.6 FPGA stage

My choice directly go to the Xilinx's FPGA because of my good engineering experience in the past with it. I oriented my research for the right FPGA to the Spartan-II 2.5V FPGA family. You can find its specification here: http://www.xilinx.com/partinfo/ds001.htm.

The Spartan-II 2.5V field-programmable gate array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200MHz. Spartan-II devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined virtex-based architecture. Features include block RAM (to 56Kbits), distributed ram (to 75,264 bits), 16 selectable I/O standards, and four DLLs.

For soldering reason I chose the PQ208 package: the only package I can solder without using a computer controlled machine.

2.2.7 Memory stage

The connection between the FPGA and the memory is quite simple (cf figure ).

The four memories are acting like one with 32 bits data width and with a depth of 18 bits of address. This configuration gives us 2MBytes of memory as buffer. Compare to our actual computers it doesn't seem a lot but it's quite enough for our real-time purpose.

TRhe memory used is from Toshiba. It's speed of 70ns was exactly what we where looking for. Here is the data-sheet: http://www.toshiba.com/taec/components/datasheet/4001a.pdf.

As you can see we are decoupling each memory with a and a capacitors. Even though this memory is working in 5V, the FPGA is 5V compliant and 3.3V output of the FPGA is more than the minimal accepted by the memory.

2.2.8 Ethernet stage

In order to interface to the ethernet, different circuit for the ethernet LAN controller like the quality semiconductor QS6611, the National Semiconductor DP83840A MII, ICS1890 MII, the Mitel Semiconductor's NWK914, the TDK Semiconductor 78Q2120 and the the SEEQ technology 80225 10/100 BASE-TX physical layer were available. Finally, the last one was chosen because of the price and quality of the documentation available.

The schematic on figure  comes from the documentation of the 80225:

The 80225 gets it's 25 MHz clock form the clock stage that we spoke about previously.

The 80225 is a highly integrated analog interface IC for twisted pair ethernet applications. The 80225 can be configured for either (100BASE-TX) or 10 MBps (10BASE-T) ethernet operation. The 80225 consists of 4B5B/Manchester encoder/decoder, scrambler/descrambler, transmitter with wave shaping and output driver, twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, auto negotiation, controller interface (MII), and serial port (MI). You can find its specification here: http://www.lsilogic.com/techlib/techdocs/networking/80225.pdf.

With the 80225, it's advised to use a pulse's H1089. You can find its specification here: http://www.pulseeng.com/pdf/4303.pdf.

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Next: 3 The VHDL program Up: 2 The Hardware Previous: 2.1 Microboard   Contents

Cedrick Rochet 2005-09-21