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3 The VHDL program for the FPGA.

In this section I am going to explain my software design in VHDL. But first of all here is a summary description of this language.

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Subsections

• 3.1 The VHDL
• 3.2 UDP
• 3.3 The Main VHDL program
• 3.4 The capture module
• 3.5 The SRAM interface module
• 3.6 The capture_udp_frame module
• 3.7 The bootp module
• 3.8 The arp module
• 3.9 The response status module
• 3.10 The mux4_1 module
• 3.11 The CRC32 module
• 3.12 The tx_frame module
• 3.13 The incoming message module
• 3.14 The read incoming message module
• 3.15 The MI interface for configuration and status

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Cedrick Rochet 2005-09-21