Presenter: Craig McGray
Mentor: Michael Gaitan
Division: Semiconductor Electronics Division, 812
Mail Stop: 8120
Sigma Xi Member: No
Stress Compensation for CMOS-Integrated
Post-processing techniques for fabrication of micro-electromechanical systems (MEMS) from standard CMOS wafers have been previously described [1-12]. These techniques make it possible to easily integrate MEMS devices on the same chip as their controlling electronics. One limitation of these techniques is that the materials used in standard CMOS processes are optimized only for electronic use, and therefore exhibit large stresses that can deform or destroy mechanical structures. In this document, a method is proposed for stress compensation of the materials used in standard CMOS processes. The method uses two thin layers of silicon nitride to offset the residual stresses resulting from the CMOS fabrication process. The thickness of these layers can be trimmed based on data from on-chip test structures, so that average and gradient stresses can be simultaneously nulled, despite inter-die variations in their magnitude.