Characterization of annealed ultrathin amorphous silicon and electrical properties of nanocrystalline silicon based memory structure

Jinwon Park, C. A. Richter, Jin Yong Kim*, N. V. Nguyen, John E. Bonevich**, and Eric M. Vogel

Semiconductor Electronics Division, NIST, Gaithersburg, MD 20899
* Ceramics Division, NIST, Gaithersburg, MD 20899
** Metallurgy Division, NIST, Gaithersburg, MD 20899

Ultrathin amorphous silicon (especially less than 10 nm thick) has tremendous potential for use in single electron memory devices, optoelectronic devices, and tunneling nanoelectronic devices. In this ultrathin regime, physical metrology issues such as thickness, morphology, structural density, and interfaces become important factors for the control of zero-dimensional or one-dimensional confined structures. We will present results of precise physical characterization of ultrathin amorphous silicon and discuss how crystalline evolution is affected by these physical properties during thermal annealing. We will also present the electrical properties of a MOS (metal-oxide-semiconductor) capacitor that has annealed amorphous silicon within the oxide gate dielectric.
Ultrathin amorphous silicon layers were deposited by low-pressure chemical vapor deposition at 550 oC. The thickness of these layers is controlled between 2 nm and 20 nm. The thickness of amorphous silicon was measured by both vacuum ultraviolet spectroscopic ellipsometry (VUV-SE) and cross section transmission electron microscopy (TEM). Atomic force microscopy (AFM) and TEM were used to characterize the microstructural changes. RMS surface roughness of amorphous silicon, as measured by AFM, is shown to be independent of film thickness. The band-gap energy measured by VUV-SE appears to increase with decreasing film thickness in the studied thickness range. Simultaneous oxidation and annealing techniques were used to crystallize the ultrathin amorphous silicon. We experimentally observe that the crystalline evolution depends upon the thickness and microstructure of the initial amorphous silicon layer. MOS capacitors were fabricated with annealed amorphous silicon within the oxide. We expect the amorphous silicon region to have crystallized as a result of the annealing. Capacitance-voltage and current-voltage characteristics suggest a large charging effect associated with the nanocrystalline silicon layer.