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Topic Area: Semiconductors
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Displaying records 31 to 40 of 147 records.
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31. Demonstration of Molecular Assembly on Silicon (100) for CMOS-Compatible Molecule-Based Electronic Devices
Topic: Semiconductors
Published: 3/7/2008
Authors: Nadine Emily Gergel-Hackett, Christopher D Zangmeister, Christina Ann Hacker, Lee J Richter, Curt A Richter
Abstract: In this work, we establish the potential of a UV-promoted direct attachment of alkanes with alcohol and thiol linkers to the CMOS-compatible silicon (100) orientation for use in closed, planar, molecular electronic devices. We develop processes for m ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=32875

32. Demonstration of a Wafer-level Hall-Mobility Measurement Technique
Topic: Semiconductors
Published: 12/3/2009
Authors: Liangchun Yu, Kin P Cheung, Vinayak Tilak, Greg Dunne, Kevin Matocha, Jason P Campbell, John S Suehle, Kuang Sheng
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=905433

33. Dependence of Electron Density on Fermi Energy in Compensated N-type Gallium Antimonide
Topic: Semiconductors
Published: 11/11/2005
Authors: Herbert S Bennett, Howard Hung
Abstract: The majority electron density as a function of the Fermi energy is calculated in zinc blende, compensated n-type GaSb for donor densities between 1016 cm-3 and 1019 cm-3. The compensation acceptor density is 1016 cm-3. These calculations solve the ch ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=31933

34. Design and Fabrication of a Copper Test Structure as a Electrical Critical Dimension Reference
Topic: Semiconductors
Published: 4/1/2006
Authors: Byron J Shulver, Andrew S Bunting, Alan Gundlach, Les I Haworth, Alan W Ross, Anthony J Snell, J. Tom Stevenson, Anthony Walton, Richard A Allen, Michael W Cresswell
Abstract: A novel copper damascene process is reported for the implementation of Electrical Critical Dimension (ECD) reference material. The method of fabrication first creates an initial 'silicon preform' whose linewidth is transfered into a trench using a si ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=32169

35. Detection of 3D Interconnect Bonding Voids by IR Microscopy
Topic: Semiconductors
Published: 2/20/2014
Authors: Jonny H?glund, Zoltan Kiss, Gyorgy Nadudvari , Zsolt Kovacs, Szabolcs Velkei, Moore Chris, Victor Vartanian, Richard A Allen
Abstract: There are a number of factors driving 3D integration including reduced power consumption, RC delay, and form factor as well as increased bandwidth. However, before these advantages can be realized, various technical and cost hurdles must be overcom ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=914474

36. Development of a Seebeck Coefficient Standard Reference Material
Topic: Semiconductors
Published: 8/7/2009
Authors: Nathan Lowhorn, Winnie K Wong-Ng, John Lu, Evan L. Thomas, Makoto Otani, Martin L Green, Neil Dilley, Jeffrey Sharp, Thanh N. Tran
Abstract: We have successfully developed a Seebeck coefficient Standard Reference Material (SRM ), Bi2Te3, that is crucial for interlaboratory data comparison and for instrument calibration. Certification measurements were performed using two different techniq ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=854458

37. Development, Performance and Applications of 4.5 kV SiC JBS Diodes
Topic: Semiconductors
Published: 3/22/2011
Author: Allen R Hefner Jr
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=908466

38. EEEL Technical Accomplishments
Series: NIST Interagency/Internal Report (NISTIR)
Report Number: 7568
Topic: Semiconductors
Published: 3/30/2009
Author: Erik M Secula
Abstract: This document describes the technical work of the Electronics and Electrical Engineering Laboratory. In this report, you will find that EEEL researchers are developing the world's most advanced sensors, providing advanced gamma ray imagers for astro ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=901701

39. EVALUATING METHODS OF SHIPPING THIN SILICON WAFERS FOR 3D STACKED APPLICATIONS
Topic: Semiconductors
Published: 11/7/2012
Authors: Richard A Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David Thomas Read, Andreas Fehk¿hrer, J¿rgen Burggraf
Abstract: An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers thinned to 100 µm or less for three-dimensional stacked integrated circuits (3DS-ICs). 3DS-ICs hold the promise of improved pe ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=912462

40. Effect of Nitrogen on Band Alignment in HfSiON Gate Dielectrics
Topic: Semiconductors
Published: 11/22/2005
Authors: Safak Sayan, Nhan V Nguyen, James R. Ehrstein, James J Chambers, Mark R Visokay, Manuel Quevedo-Lopez, Luigi Colombo, T Yoder, Igor Levin, Daniel Fischer, M Paunescu, Ozgur Celik, Eric Garfunkel
Abstract: We have studied the band alignment of HfSiO and HfSiON films by soft x-ray photoemission (SXPS), oxygen K-edge x-ray absorption (XAS), and spectroscopic ellipsometry. Nitridation of HfSiO reduced the band gap by 1.50+- 0.05eV and the valence and cond ...
http://www.nist.gov/manuscript-publication-search.cfm?pub_id=32000



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