Special for SEMICON West 2008, July 14-18, 2008

‘Nanoglassblowing’ Seen as Boon to Study of Individual Molecules

Left: Schematic of a T-junction nanofluidic device with a "nanoglassblown" funnel-shaped entrance to a nanochannel. The funnel tapers down to 150 micrometers (about the diameter of a human hair) at the nanochannel entrance. Right: Photomicrograph of the T-junction with the first section of the nanochannel visible at the bottom. The colors are a white light interference pattern caused by the changing depth of the curved glass funnel. Credit: Elizabeth Strychalski, Cornell University View hi-resolution image

While the results may not rival the artistry of glassblowers in Europe and Latin America, researchers at the National Institute of Standards and Technology (NIST) and Cornell University have found beauty in a new fabrication technique called “nanoglassblowing” that creates nanoscale (billionth of a meter) fluidic devices used to isolate and study single molecules in solution—including individual DNA strands. The novel method is described in a paper posted in the journal Nanotechnology.*

Traditionally, glass micro- and nanofluidic devices are fabricated by etching tiny channels into a glass wafer with the same lithographic procedures used to manufacture circuit patterns on semiconductor computer chips. The planar (flat-edged) rectangular canals are topped with a glass cover that is annealed (heated until it bonds permanently) into place. About a year ago, the authors of the Nanotechnology paper observed that in some cases, the heat of the annealing furnace caused air trapped in the channel to expand the glass cover into a curved shape, much like glassblowers use heated air to add roundness to their work. The researchers looked for ways to exploit this phenomenon and learned that they could easily control the amount of “blowing out” that occurred over several orders of magnitude.

As a result, the researchers were able to create devices with “funnels” many micrometers wide and about a micrometer deep that tapered down to nanochannels with depths as shallow as 7 nanometers—approximately 1,000 times smaller in diameter than a red blood cell. The nanoglassblown chambers soon showed distinct advantages over their planar predecessors.

“In the past, for example, it was difficult to get single strands of DNA into a nanofluidic device for study because DNA in solution balls up and tends to bounce off the sharp edges of planar channels with depths smaller than the ball,” says Cornell’s Elizabeth Strychalski. “The gradually dwindling size of the funnel-shaped entrance to our channel stretches the DNA out as it flows in with less resistance, making it easier to assess the properties of the DNA,” adds NIST’s Samuel Stavis.

Future nanoglassblown devices, the researchers say, could be fabricated to help sort DNA strands of different sizes or as part of a device to identify the base-pair components of single strands. Other potential applications of the technique include the manufacture of optofluidic elements—lenses or waveguides that could change how light is moved around a microchip—and rounded chambers in which single cells could be confined and held for culturing.

This work was supported in part by Cornell’s Nanobiotechnology Center, part of the National Science Foundation’s Science and Technology Center Program. It was performed while Samuel Stavis held a National Research Council Research Associateship Award at NIST.

*E.A. Strychalski, S.M. Stavis, and H.G. Craighead. Non-planar nanofluidic devices for single molecule analysis fabricated using nanoglassblowing. Nanotechnology, Posted online the week of June 17, 2008.

Technical Contact: Elizabeth Strychalski, eas58@cornell.edu, (607) 255-6286; Samuel Stavis, sam.stavis@nist.gov, (301) 975-3246

Media Contact: Michael E. Newman, michael.newman@nist.gov, (301) 975-3025

‘Electron Trapping’ May Impact Future Microelectronics Measurements

Using an ultra-fast method of measuring how a transistor switches from the “off” to the “on” state, researchers at the National Institute of Standards and Technology (NIST) recently reported that they have uncovered an unusual phenomenon that may impact how manufacturers estimate the lifetime of future nanoscale electronics.

The transistor is one of the basic building blocks of modern electronics, and the life expectancy or reliability of a transistor is often projected based on the response to an accelerated stress condition. Changes in the transistor’s threshold voltage (the point at which it switches on) are typically monitored during these lifetime projections. The threshold voltage of certain types of transistors (p-type) is known to shift during accelerated stresses involving negative voltages and elevated temperatures, a characteristic known as “negative bias temperature instability” (NBTI). This threshold voltage shift recovers to varying degrees once the stress has ended. This “recovery” makes the task of measuring the threshold voltage shift very challenging and greatly complicates the prediction of a transistor’s lifetime.

As semiconductor devices reach nanoscale (billionth of a meter) dimensions, measuring this device reliabil-ity accurately becomes more important because of new materials, new structures, higher operating temperatures, and quantum mechanical effects. Many NBTI studies show that the accuracy of the measured threshold voltage shift (and consequent accuracy of the lifetime prediction) depends strongly on how quickly the threshold voltage can be measured after the stress is finished. So, NIST engineers began making threshold voltage measurements at very fast speeds, leaving as little as 2 microsceconds (millionths of a second) between measurements instead of the traditional half-second interval. What they observed was surprising.

“We found that NBTI recovery not only returned the threshold voltage to its pre-stressed state but briefly passed this mark and temporarily allowed the transistor to behave better than the pre-stressed state,” says Jason Campbell, a member of the NIST team (that includes Kin Cheung and John Suehle) who presented this finding at the recent Symposium on VLSI Technology in Hawaii. The NBTI effect is generally believed to result from the buildup of positive charges, he explained, but the new observations at NIST indicate the presence of negative charge as well. NIST’s ultra-fast and ultra-sensitive measurements revealed that during recovery, the positive charges dissipated faster than the electrons, giving the system a momentary negative charge and heightened conductivity.

Campbell says that to date, transistor manufacturers only consider the accumulation of positive charges to predict the longevity of their microelectronics devices. “But as these systems get smaller and smaller, the electron trapping phenomenon we observed will need to be considered as well to ensure that transistor lifetime predictions stay accurate,” he says. “Our research will now focus on developing and refining the ability to measure that impact.”

Technical Contact: Jason Campbell, jason.campbell@nist.gov, (301) 975-8308

Media Contact: Michael E. Newman, michael.newman@nist.gov, (301) 975-3025

Exposing the Sensitivity of Extreme Ultraviolet Photoresists

NIST researchers exposed a 300 mm silicon wafer with incrementally increasing doses of extreme ultraviolet light (EUV) in 15 areas. After the wafer was developed, the team determined that the seventh exposure was the minimum dose required (E0) to fully remove the resist. Credit: NIST View hi-resolution image

Researchers at the National Institute of Standards and Technology (NIST) have confirmed that the photoresists used in next-generation semiconductor manufacturing processes now under development are twice as sensitive as previously believed. This finding, announced at a recent workshop,* has attracted considerable interest because of its implications for future manufacturing. If the photoresists are twice as sensitive as previously thought, then they are close to having the sensitivity required for high volume manufacturing, but the flip side is that the extreme ultraviolet optical systems in the demonstration tools currently being used are only about half as effective as believed.

Extreme ultraviolet lithography (EUVL) is a process analogous to film photography. A silicon wafer is coated with photoresist and exposed to EUV light that reflects off a patterned “photomask.” Where the light strikes the resist it changes the solubility of the coating. When developed, the soluble portions wash away leaving the same pattern exposed on the silicon surface for the processing steps that ultimately create microcircuits.

The drive to make circuits with ever smaller features has pushed manufacturers to use shorter and shorter wavelengths of light. EUVL is the next step in this progression and requires developing both suitable light sources and photoresists that can retain the fine details of the circuit, balancing sensitivity, line edge roughness, and spatial resolution. NIST researcher Steve Grantham says that optical lithography light sources in use today emit light with a wavelength of about 193 nanometers, which borders on optical wavelengths. EUVL sources produce light with wavelengths about an order of magnitude smaller, around 13.5 nanometers. Because this light does not travel through anything—including lenses—mirrors have to be used to focus it.

Until recently, EUV photoresist sensitivity was referenced to a measurement technique developed at Sandia National Labs in the 1990s. Late in 2007, scientists at the Advanced Light Source at Lawrence Berkeley National Laboratory in Berkeley, Calif., used a NIST-calibrated photodetector to check the standard. Their detector-based measurements indicated that the resist’s sensitivity was about twice that of the resist-based calibration standard.

Following on the intense interest that these results generated when the Berkeley group presented them at a conference in February, the Intel Corporation asked scientists at NIST to make their own independent determination of the EUVL resist sensitivity to validate the results. Measurements conducted at the NIST SURF III Synchrotron Ultraviolet Radiation Facility agreed with those of the Berkeley group. The fact that the photo-resist is now known to be twice as sensitive to the EUV light implies that half as much light energy as had been expected is arriving at the wafer.

“These results are significant for a technology that faces many challenges before it is slated to become a high-volume manufacturing process in 2012,” Grantham says. “It should open the eyes of the industry to the need for accurate dose metrology and the use of traceable standards in their evaluations of source and lithography tool performance.”

*S. Grantham, C. Tarrio, R. E. Vest, T. B. Lucatorto, A. Novembre, M. Cangemi, V. Prabhu, K.W. Choi, M. Chandhok, T. Younkin, and J.S. Clarke. SEMATECH EUV Source Workshop, Bolton Landing, N.Y., May 12, 2008.

Technical Contact: Steve Grantham, steven.grantham@nist.gov, (301) 975-5528

Media Contact: Mark Esser, mark.esser@nist.gov, (301) 975-8735

Making a Good Impression: Nanoimprint Lithography Tests at NIST

Electron micrograph shows a cross-section of a typical SOG microcircuit feature. Nanoporous regions in the interior are lighter. The process forms a dense, stronger skin about 2 nanometers thick on the outside. (Color added for clarity.) Credit: NIST View hi-resolution image

In what should be good news for integrated circuit manufacturers, recent studies by the National Institute of Standards and Technology (NIST) have helped resolve two important questions about an emerging microcircuit manufacturing technology called nanoimprint lithography—yes, it can accurately stamp delicate insulating structures on advanced microchips, and, no, it doesn’t damage them, in fact it makes them better.

An emerging manufacturing technique, nanoimprint lithography (NIL) is basically an embossing process. A stamp with a nanoscale pattern in its surface is pressed into a soft film on the surface of a semiconductor wafer. The film is hardened, usually by heating or exposure to ultraviolet light, and the film retains the impressed pattern from the stamp. The process is astonishingly accurate. NIL has been used to create features as small as 10 nanometers across with relatively complex shapes.

NIL is being eyed in particular for building the complexly patterned insulating layers sandwiched between layers of logic devices in future generations of integrated circuits. State-of-the-art semiconductors contain over a billion transistors, packed together into a footprint of silicon that is no bigger than a few square centimeters. Several miles of nanoscale copper wiring are required to connect the devices, and these wires must be separated by a highly efficient insulator. One candidate is a porous glassy material called SOG,* which can be applied as a thin fluid film. When heated, SOG turns into a thin glass film laced with nanometer pores that enhance the electrical insulation. But SOG is relatively delicate, and the conventional photoresist etching process used to cut trenches for the wiring can compromise it. NIL, on the other hand, might be able to pattern SOG layers with wiring trenches and eliminate several time-consuming and expensive photolithography steps if it could pattern the film accurately and do so without destroying the delicate nanopore lacework.

In another paper,** NIST materials scientists addressed the first question. Using sensitive X-ray measurements they demonstrated that NIL could be used on a functional SOG material to transfer patterns with details finer than 100 nanometers with minimal distortion due to the processing. They extend this work*** to study the effect of the embossing process on the nanopore structure in the glass. Using a combination of techniques to measure the distribution of nanopores in the insulator material, they found that the NIL embossing process actually has a beneficial effect—it increases the population of small pores, which improve performance, reduces the population of larger pores that can cause problems and creates a thin, dense protective skin across the surface of the material. All of these effects are highly attractive for minimizing short circuits in semiconductor devices.

Taken together, the two papers suggest that nano-imprint lithography can produce superior nanoporous insulator layers in advanced semiconductor devices with significantly fewer—and easier—processing steps than conventional lithography.

* “Spin-on organosilicate glass”
**H.W. Ro, R.L. Jones, H. Peng, D.R. Hines, H-J. Lee, E.K. Lin, A. Karim, D.Y. Yoon, D.W. Gidley, and C.L. Soles. The direct patterning of nanoporous interlayer dielectric insulator films by nanoimprint lithography. Advanced Materials. 2007, 19, 2919-2924.
***H.W. Ro, H. Peng, K.-i. Niihara, H.-J. Lee, E.K. Lin, A. Karim, D.W. Gidley, H. Jinnai, D.Y. Yoon, and C.L. Soles. Self-sealing of nanoporous low dielectric constant patterns fabricated by nanoimprint lithography. Advanced Materials. 2008, 20, 1934-1939.

Technical Contact: Hyun Wook Ro, hyun.ro@nist.gov, (301) 975-4736

Media Contact: Michael Baum, michael.baum@nist.gov, (301) 975-2763

NIST Team Proves Bridge from Conventional to Molecular Electronics Possible

Side and top views of the NIST molecular resistor. Above are schematics showing a cross-section of the full device and a close-up view of the molecular monolayer attached to the CMOS-compatible silicon substrate. Below is a photomicrograph looking down on an assembled resistor indicating the location of the well. Credit: NIST View hi-resolution image

Researchers at the National Institute of Standards and Technology (NIST) have set the stage for building the “evolutionary link” between the microelectronics of today built from semiconductor compounds and future generations of devices made largely from complex organic molecules. In a paper published in the Journal of the American Chemical Society,* a NIST team demonstrates that a single layer of organic molecules can be assembled on the same sort of substrate used in conventional microchips.

The ability to use a silicon crystal substrate that is compatible with the industry-standard CMOS (complementary metal oxide semiconductor) manufacturing technology paves the way for hybrid CMOS-molecular device circuitry—the necessary precursor to a “beyond CMOS” totally molecular technology—to be fabricated in the near future.

Scientists classify crystal structures by the particular plane or “face” cutting through the crystal that is exposed. Most research to date on silicon substrates for molecular electronic devices has been done with a crystal orientation that is convenient for organic molecules but incompatible with CMOS technologies. For their electronic device, the NIST team first demonstrated that a good quality monolayer of organic molecules could be assembled on the silicon orientation common to industrial CMOS fabrication, verifying this with extensive spectroscopic analysis.

They then went on to build a simple but working molecular electronic device—a resistor—using the same techniques. A single layer of simple chains of carbon atoms tethered on their ends with sulfur atoms were deposited in tiny 100-nanometer deep wells on the silicon substrate and capped with a layer of silver to form the top electrical contact. The use of silver is a departure from other molecular electronic studies where gold or aluminum has been used. Unlike the latter two elements, silver does not displace the monolayer or impede its ability to function.

The NIST team fabricated two molecular electronic devices, each with a different length of carbon chain populating the monolayer. Both devices successfully resisted electrical flow with the one possessing longer chains having the greater resistance as expected. A control device lacking the monolayer showed less resistance, proving that the other two units did function as nonlinear resistors.

The next step, the team reports, is to fabricate a CMOS-molecular hybrid circuit to show that molecular electronic components can work in harmony with current microelectronics technologies.

This work was funded in part by the NIST Office of Microelectronics Programs and the Defense Advanced Research Projects Agency (DARPA) MoleApps Program.

*N. Gergel-Hackett, C.D. Zangmeister, C.A. Hacker, L.J. Richter, and C.A. Richter. Demonstration of molecular assembly on Si (100) for CMOS-compatible molecular-based electronic devices. Journal of the American Chemical Society. 2008, 130, 13, pp 4259-4261.

Technical Contact: Nadine Gergel-Hackett, nadine.gergelhackett@nist.gov, (301) 975-8755

Media Contact: Michael E. Newman, michael.newman@nist.gov, (301) 975-3025

Directed Self-Ordering of Organic Molecules for Electronic Devices

Optical micrographs of typical FET structures in the NIST/Penn State/UK experiments show the effect of pretreating contacts to promote organic crystal formation. Treated structure (l) shows crystal structure extending from the rectangular contacts and merging in the channel in contrast to untreated contacts (r). Credit: NIST View hi-resolution image of image on left View hi-resolution image of image on right

A simple surface treatment technique demonstrated by a collaboration between researchers at the National Institute of Standards and Technology (NIST), Penn State, and the University of Kentucky potentially offers a low-cost way to mass produce large arrays of organic electronic transistors on polymer sheets for a wide range of applications including flexible displays, “intelligent paper” and flexible sheets of biosensor arrays for field diagnostics.

The team’s paper* describes how a chemical pretreatment of electrical contacts can induce self-assembly of molecular crystals to both improve the performance of organic semiconductor devices and provide electrical isolation between devices.

Organic electronic devices are inching towards the market. Compounds with tongue-twisting names such as “5,11-bis(triethylsilylethynyl) anthradithiophene” can be designed with many of the electrical properties of more conventional semiconductors. But unlike traditional semiconductors that require high-temperature processing steps, organic semiconductor devices can be manufactured at room temperature. They could be built on flexible polymers instead of rigid silicon wafers. Magazine-size displays that could be rolled up or folded to pocket size and plastic sheets that incorporate large arrays of detectors for medical monitoring or diagnostics in the field are just a couple of the tantalizing possibilities.

One unsolved problem is how to manufacture them efficiently and at low cost. Large areas can be coated rapidly with a thin film of the organic compound in solution, which dries to a semiconductor layer. But for big arrays like displays, that layer must be patterned into electrically isolated devices. Doing that requires one or more additional steps that are costly, time consuming and/or difficult to do accurately.

The NIST team and their partners studied the organic version of a workhorse device—the field effect transistor (FET)—that commonly is used as a switch to, for example, turn pixels on and off in computer displays. The essential structure consists of two electrical contacts with a channel of semiconductor between them. The researchers found that by applying a specially tailored pretreatment compound to the contacts before applying the organic semiconductor solution they could induce the molecules in solution to self-assemble into well-ordered crystals at the contact sites. These structures grow outwards to join across the FET channel in a way that provides good electrical properties at the FET site, but farther away from the treated contacts the molecules dry in a more random, helter-skelter arrangement that has dramatically poorer properties—effectively providing the needed electrical isolation for each device without any additional processing steps. The work is an example of the merging of device structure and function that may enable low cost manufacturing, and an area where organic materials have important advantages.

In addition to its potential as a commercially important manufacturing process, the authors note that this chemically engineered self-ordering of organic semiconductor molecules can be used to create test structures for fundamental studies of charge transport and other important properties of a range of organic electronic systems.

*D.J. Gundlach, J.E. Royer, S.K. Park, S. Subramanian, O.D. Jurchescu, B.H. Hamadani, A.J. Moad, R.J. Kline, L.C. Teague, O. Kirillov, C.A. Richter, J.G. Kushmerick, L.J. Richter, S.R. Parkin, T.N. Jackson, and J.E. Anthony. Contact-induced crystallinity for high-performance soluble acene-based transistors and circuits. Nature Materials Advanced Online Publication, 17 February 2008.

Technical Contact: David Gundlach, david.gundlach@nist.gov, (301) 975-2048

Media Contact: Michael Baum, michael.baum@nist.gov, (301) 975-2763

NIST Demos Industrial-Grade Nanowire Device Fabrication

Nanowire electronics: (Top) Optical image shows metal electrodes attached to zinc oxide nanowires using the NIST technique. Dark spots near the center are the gold pads that start nanowire growth; red arrow shows direction of growth. Scale bar is 50 micrometers long. (Bottom) Scanning electron microscope image shows electrodes connected to group of nanowires. Scale bar is five micrometers long. Credit: NIST View hi-resolution image (top) View hi-resolution image (bottom)

In the growing catalog of nanoscale technologies, nanowires—tiny rows of conductor or semiconductor atoms—have attracted a great deal of interest for their potential to build unique atomic-scale electronics. But before you can buy some at your local Nano Depot, manufacturers will need efficient, reliable methods to build them in quantity. Researchers at the National Institute of Standards and Technology (NIST) believe they have one solution—a technique that allows them to selectively grow nanowires on sapphire wafers in specific positions and orientations accurately enough to attach contacts and layer other circuit elements, all with conventional lithography techniques. They detailed their results in a 2007 paper.*

Despite their name, nanowires are more than just electrical connectors. Researchers have used nanowires to create transistors like those used in memory devices and prototype sensors for gases or biomolecules.

However, working with objects only tens of nanometers wide is challenging. A common approach in the lab is to grow nanowires like blades of grass on a suitable substrate, mow them off and mix them in a fluid to transfer them to a test surface, using some method to give them a preferred orientation. When the carrier fluid dries, the nanowires are left behind like tumbled jackstraws.

Using scanning probe microscopy or similar tools, researchers hunt around for a convenient, isolated nanowire to work on, or place electrical contacts without knowing the exact positions of the nanowires. It’s not a technique suitable for mass production.

Building on earlier work to grow nanowires horizontally on the surface of wafers, NIST researchers used conventional semiconductor manufacturing techniques to deposit small amounts of gold in precise locations on a sapphire wafer. In a high-temperature process, the gold deposits bead up into nanodroplets that act as nucleation points for crystals of zinc oxide, a semiconductor. A slight mismatch in the crystal structures of zinc oxide and sapphire induces the semiconductor to grow as a narrow nanowire in one particular direction across the wafer. Because the starting points and the growth direction are both well known, it is relatively straightforward to add electrical contacts and other features with additional lithography steps.

As proof of concept, the NIST researchers have used this procedure to create more than 600 nanowire-based transistors, a circuit element commonly used in digital memory chips, in a single process. In the prototype process, they report, the nanowires typical grew in small bunches of up to eight wires at a time, but finer control over the size of the initial gold deposits should make it possible to select the number of wires in each position. The technique, they say, should allow industrial-scale production of nanowire-based devices.

*B. Nikoobakht. Toward industrial-scale fabrication of nanowire-based devices. Chem. Mater., ASAP Article 10.1021/cm071798p S0897-4756(07)01798-X. Web Release Date: Oct. 9, 2007.

Technical Contact: Babak Nikoobakht, babak.nikoobakht@nist.gov, (301) 975-3230

Media Contact: Michael Baum, michael.baum@nist.gov, (301) 975-2763

Measurement Innovations Add Up to Big Savings for Semiconductors

Russell Hajdaj prepares silicon wafers that will be "baked" as part of the processing required for producing new types of semiconductor devices. Credit: Copyright Robert Rathe View hi-resolution image

A report* from the National Institute of Standards and Technology (NIST) shows that investment in measurement science has and will continue to have a dramatic effect on innovation, productivity, growth, and competitiveness in and among high technology sectors. Citing the semiconductor industry as a case in point, the analysis, prepared for NIST by RTI International (RTI), estimates that the $12 billion spent on advancing measurement capabilities during the decade beginning in 1996 will have saved that sector more than $51 billion in scrap and rework costs by 2011—a net benefit of approximately $39 billion.

RTI estimates that for every dollar spent on measurement, the industry as a whole saw a $3.30 return. (Dollar amounts represent 2006 dollars adjusted for inflation.) The report found that the strategic focus on measurement technologies pursued by the International Technology Roadmap for Semiconductors (ITRS), a consortium of chip manufacturers and related stakeholders, benefited both the industry and consumers through the reduction of defect rates and the miniaturization of feature size. The advances fostered through this effort, among others, resulted in lower costs, higher product quality and ever faster processing speeds.

Measurement technology has allowed the industry to keep up with “Moore’s Law,” which predicts the number of transistors per chip will double every two years. By the early 1990s, the industry realized it would no longer be possible to satisfy this benchmark without the ability to manipulate nanoscale-sized features. The report credits the initiative to augment nanoscale measurement capabilities outlined in the ITRS and its predecessor as one of the factors that helped manufacturers to increase the possible number of transistors per chip from 3.1 million in 1996 to 1.7 billion in 2006 while making marked improvements in quality, design, software and interoperability.

The report underlines the importance of measurement science to the semiconductor industry and highlights several areas that need further improvement if the industry is to stay on pace. These areas include the need for new standards for measuring features lengths at 32 nanometers, new techniques for controlling radio-frequency electromagnetic energy and high-frequency magnetic fields, and better chemical and materials standards, as well as new and more accurate calibration, interoperability, and test standards.

RTI gathered the information for this analysis through surveys and other means. The answered queries accounted for more than 80 percent of the semiconductor industry, and the results were taken to be representative of the industry as a whole. The results may also be viewed as conservative in that RTI was able to quantitatively estimate productivity impacts but not increases in quality.

*Economic Impact of Measurement in the Semiconductor Industry is available on the NIST Web site at www.nist.gov/director/planning/policy_studies.htm.

Technical Contact: Gregory Tassey, gregory.tassey@nist.gov, (301) 975-2663

Media Contact: Mark Esser, mark.esser@nist.gov, (301) 975-8735

Good Vibrations Probe Innards of Molecular Electronic Junctions

NIST researchers determined that the organic molecules in the middle of this simple silicon-based molecular “sandwich” pass electric current through these junctions by carefully measuring the minute changes in molecular vibrations. Credit: NIST View hi-resolution image

Using an unusual spectroscopic technique, researchers at the National Institute of Standards and Technology (NIST) have provided the most convincing evidence yet that current is flowing through a simple silicon-based molecular “sandwich,” which is the most basic structure of molecular electronics. The work* is an important step toward realizing the dream of organic molecule-based electronics that could enable much denser, cheaper computer memories and other replacements of traditional electronic devices.

“The ultimate in miniaturization is the molecule,” explains NIST’s Curt Richter. “The hope is that a single molecule will one day be able to act as an electrical component such as a diode or a resistor with the ultimate goal being shrinking computer chips.”

For the past few years, scientists have been building and testing structures made of a hybrid of traditional silicon-based components and more futuristic molecule-based components. The typical junction is a sandwich of a metallic contact layer, a layer of organic compound just a single molecule thick arranged like bristles on a brush, and a substrate of silicon. Richter says that while the electric current seems to pass through the molecules, the current could be finding a way around it or the molecules could have been damaged in fabrication. Scientists want to know what is really happening inside this “black box.”

NIST researchers tried a little-used technique called inelastic electron tunneling spectroscopy (IETS) that measures the vibrations of the molecules inside the junction. “Each molecule has its own vibrational fingerprint,” says Wenyong Wang, adding “IETS acts as our eyes to see what is inside the black box.” An earlier paper by Wang and his colleagues at Yale University set IETS as a standard technique to prove that molecules remain intact in metal-based molecular electronic devices.

Colleagues at Purdue University provided three types of silicon-molecule-metal junctions that are a few micrometers large. The small molecules researchers used were octadecane, nitrobenzene, and diethylaminobenzene.

Each silicon-molecule-metal device was cooled to cryogenic temperatures. Wang carefully measured the minute changes in the current passing through the junctions, and these current changes were then related to specific molecular vibrations. Thus, the researchers verified the existence of the molecules and that the electric current passed through them.

NIST physicists plan to continue research into silicon-molecule-metal junctions. “Once we understand the physics of the devices, we can begin to assess how viable the technology is and also determine which molecules may supply the best chance for a technological breakthrough,” says Richter.

*W. Wang, A. Scott, N. Gergel-Hackett, C.A. Hacker, D.B. Janes, and C.A. Richter. Probing molecules in integrated silicon-molecule-metal junctions by inelastic tunneling spectroscopy. ACS Nano Letters, 8, 478 (2008).

Technical Contact: Wenyong Wang, wenyong.wang@nist.gov, (301) 975-3377

Media Contact: Evelyn Brown, evelyn.brown@nist.gov, (301) 975-5661

NIST Team Develops Novel Method for Nanostructured Polymer Thin Films

(Top L.) Schematic of the NIST 'cold zone' annealing process for polymer thin films on a semiconductor wafer. Experiment images are color-coded to show regions with different cylinder orientations, as measured by atomic force microscopy. Relatively rapid transit times (top r.) leave a jumble of different regions that become largely homogeneous at slower speeds (r.).
Credit: NIST View hi-resolution image

All researchers at the National Institute of Standards and Technology (NIST) wanted was a simple, quick method for making thin films of block copolymers or BCPs (chemically distinct polymers linked together) in order to have decent samples for taking measurements important to the microelectronics industry. What they got for their efforts, as detailed in Nano Letters,* was an unexpected bonus: a unique annealing process that may make practical the use of BCP thin films for patterning nanoscale features in next-generation microchips and data storage devices.

BCP thin films have been highly desired by semiconductor manufacturers as patterns for laying down very fine features on microchips, such as arrays of tightly spaced, nanoscale lines. Annealing certain BCP films—a controlled heating process—causes one of the two polymer components to segregate into regular patterns of nanocylinder lines separated by distances as small as 5 nanometers or equally regular arrays of nanoscale dots. Chemically removing the other polymer leaves the pattern behind as a template for building structures on the microchip.

In traditional oven annealing the quality of the films is still insufficient even after days of annealing. A process called hot zone annealing—where the thin film moves at an extremely slow speed through a heated region that temporarily raises its temperature to a point just above that at which the cylinders become disordered—has previously been used for creating highly ordered BCP thin films with a minimum of defects but little orientation control. For some polymer combinations, the order-disorder transition temperature is so high that it is virtually impossible for manufacturers to heat them sufficiently without degradation occurring.

To eliminate the time and temperature restraints without losing the order yielded by hot zone annealing, the NIST researchers developed a “cold zone” annealing system where the polymers are completely processed well below their order-disorder transition temperature. Properly controlled, the lower-temperature processing not only works with BCPs for which hot-zone annealing is impractical, but, as the NIST experiments showed, also repeatedly produces a highly ordered thin film in a matter of minutes. NIST researchers also discovered that the alignment of the cylinders was controlled by the “cold zone” annealing conditions. Because it is simple, yields consistent product quality and has virtually no limitations on sample dimensions, the NIST method is being evaluated by microelectronic companies to fabricate highly ordered sub 30 nanometer features.

The next step, the NIST researchers say, is to better understand the fundamental processes that make the cold zone annealing system work so well and refine the measurements needed to evaluate its performance.

*B.C. Berry, A.W. Bosse, J.F. Douglas, R.L. Jones, and A. Karim. Orientational order in block copolymer films zone annealed below the order-disorder transition temperature. Nano Letters. 2007, vol. 7, no. 9, 2789-2794.

Technical Contact: Brian Berry, brian.berry@nist.gov, (301) 975-5696

Media Contact: Michael E. Newman, michael.newman@nist.gov, (301) 975-3025

Catching Waves: Measuring Self-Assembly in Action

Schematic of the monolayer self-assembly process studied by the NIST/NCSU team. The silicon substrate is approximately 1 x 5 cm in dimensions. The source (left) is a mixture of organosilane (OS) molecules and paraffin oil (to control the evaporation rate.) The whole system is enclosed in a Petri dish. The concentration of OS molecules is higher near the source and the ordering process initiates near this region. Molecules behind the advancing self-assembly front are relatively ordered, while molecules ahead of the front are engulfed and incorporated as the front reaches them. The molecules at the leading edge of the front are less ordered and this region becomes broader as the front advances—this is the key phenomenon measured in the experiment. Credit: NIST View hi-resolution image Click to view movie of a mean field reaction-diffusion model of the monolayer self-assembly process. High-resolution measurements reveal that the S-shaped interfacial region of the self-assembly wavefront becomes progressively rougher as it advances, a feature not captured by the model. (Requires Realplayer or Windows Media Player.)

By making careful observations of the growth of a layer of molecules as they gradually cover the surface of a small silicon rectangle, researchers from the National Institute of Standards and Technology (NIST) and North Carolina State University (NCSU) have gained basic insights into how self-propagating self-assembly wave fronts develop and have produced the first experimental verification of recently improved theoretical models of such systems. In addition, the researchers say, the results reported in the Proceedings of the National Academy of Sciences* should be important to understanding self-propagating chemical reactions and ordering and self-assembly phenomena in situations involving confinement, such as thin films and the porous internal geometries of many materials, such as rocks and cement.

Systems that are transformed by so-called ‘self-propagating’ or ‘autocatalytic’ wave fronts actually are very common. Diverse molecular processes, and even social processes and population dynamics, often can be described in terms of fundamental ‘entities’ that undergo changes randomly on an individual level but at large scales exhibit some regular motion or pattern formation as they collectively move from some unstable situation to a relatively stable state. Mathematicians have developed a highly successful basic model for such processes, called mean field theory. The same basic equations describe, for example, the spread of advantageous genes in an animal population, the growth of brain tumors, wound healing, flame propagation, the spread of contagious epidemics, the spread of Neolithic farming techniques, and chemical reaction fronts and nerve propagation—all phenomena that grow outward on waves of change.

In recent years, simulations and theoretical arguments have suggested that small fluctuations can significantly influence the advance of these wave fronts as they grow. In the simple case of growth of a layer of molecules by self-assembly, this would lead to a progressive roughening of the interface between the ordered and disordered regions. This phenomenon is completely missed in the classical mean field theory, raising important questions about the applicability of these and philosophically similar models to describe propagating fronts under general conditions.

To provide experimental verification of this phenomenon in a real system, the NIST/NCSU team examined the spontaneous assembly of organosilane molecules into a monolayer film on an oxidized silicon surface. If a supply of the carbon-silicon-based molecules is placed along one edge of a treated silicon wafer, under controlled conditions, the organosilane molecules spontaneously organize themselves into a well-ordered layer, creating a carpet-like layer on the silicon that advances from the edge of the wafer at a constant velocity. The technique involved was developed in the 1990s as a simple way to create substrates with a gradually changing surface-energy gradient, a useful experimental tool for surface scientists. The system lends itself to high-resolution measurement because the process is slow enough to allow highly precise, quantitative measurements of the layer as it advances using a high-resolution synchrotron X-ray technique. The team found wavelike ordering, as expected from classical theory, but with the interface of the growing front broadened in time, as predicted by the recent theoretical modeling, but in contrast with classical theory.

The work was funded in part by the National Science Foundation.

*J.F. Douglas, K. Efimenko, D.A. Fischer, F.R. Phelan, and J. Genzer. Propagating waves of self-assembly in organosilane monolayers. Proceedings of the National Academy of Sciences, 2007 104: 10324-10329.

Technical Contact: Jack Douglas, jack.douglas@nist.gov, (301) 975-6779

Media Contact: Michael Baum, michael.baum@nist.gov, (301) 975-2763