• Method Is a Welcome ‘Wrinkle’ for Testing Microchip Insulators
• NIST’s New Nanofabrication Facility to Aid Chip Industry
• A Safer Way to Make Metal Nanospheres
• New Standards to Improve Measurements of Microdevices
• Lack of Supply Chain Standards Costing Billions of Dollars
• NIST Helps Chip Industry Get Its Timing Right
• Scaling Friction Down to the Nano/Micro Realm
• ‘Liquid Lenses’ to Improve Semiconductor Lithography
• New Cryogenic Refrigerator Dips Chips into a Deep Freeze
• Delving into Defects Spurs Prospects for Chip Insulator

For more information, go to www.nist.gov/public_affairs/semiconductor.htm.

Method Is a Welcome ‘Wrinkle’ for Testing Microchip Insulators

With a new high-throughput testing method developed at the National Institute of Standards and Technology (NIST), the semiconductor industry can step up its pursuit of nanoporous thin films that can survive the rigors of processing and still protect chip layers and devices from short-circuiting.

In the August issue of Nature Materials,* NIST researchers and their IBM collaborators describe how the quantitative measurement approach can be used to assess the mechanical properties of large assortments of candidate insulating films. New so-called low dielectric constant, or low-k, films are needed to provide ever-greater levels of protection against on-chip leakages of electric current that could threaten future chip performance.

Dispersing nanopores in thin films can improve their effectiveness as electrical insulators, but often at a price. The tiny holes also can compromise the films’ strength, making them vulnerable to damage during processing.

Smaller than a box of tissues, a NIST-devised instrument can measure and analyze the strength and stiffness of a thin-film sample in about 2 seconds, as compared to several minutes for nanoindentation and other conventional approaches. Hundreds or even a few thousand systematically varying samples can be evaluated in rapid succession.

The new method entails mounting a postage-stamp-sized assortment of incrementally varying thin films on a strip of silicone rubber about the size of a Band-Aid. Placed on a custom-built stage, the combination of sample array and soft substrate then is stretched or compressed. At a critical point of instability, a sample buckles, wrinkling like a piece of corrugated cardboard.

Situated beneath the stage, a laser beams through the sample and a camera captures the scattered light. From the resulting diffraction pattern, the buckling wavelength, or distance between the peaks of adjacent wrinkles, is determined. A series of mathematical calculations relates this wavelength to the elastic modulus of the sample, which corresponds to the strength of the material.

Other applications for the test method, suggests Christopher Stafford, a NIST polymer scientist, include evaluations of new photoresist masks that will be used with next-generation ultraviolet light sources. The technique also should be useful for assessing the mechanical properties of nanotechnology devices made with still-experimental fabrication methods, such as nano-imprint lithography.

* “A buckling-based metrology for measuring the elastic moduli of polymeric thin films,” available at Nature Materials, Advance Online Publication: http://www.nature.com/naturematerials.

Technical Contact: Chris Stafford, (301) 975-4368

Media Contact: Mark Bello, (301) 975-3776

NIST’s New Nanofabrication Facility to Aid Chip Industry

On June 21, the National Institute of Standards and Technology (NIST) dedicated a new $235 million Advanced Measurement Laboratory (AML) that includes a full wing of state-of-the art clean room space, the Nanofabrication Facility. The facility will provide researchers at NIST working on a variety of semiconductor and other nanotechnology research the ability to fabricate prototypical nanoscale test structures, reference materials, and electronic devices.

Considered the most technically advanced research facility of its kind in the world, the AML supports some of the world’s most delicate experiments in nanotechnology and metrology. The new facility allows NIST to provide the sophisticated measurements and standards needed by U.S. industry and the scientific community.

The shared-access, nanofabrication user facility includes about 1,672 square meters (18,000 square feet) of raised floor, class 100/ISO 5 laboratory space, (i.e., less than 100 particles larger than 0.5 microns in each cubic foot of air). Individual laboratory modules within the facility can be upgraded to class 10/ISO 4. A gallery area adjacent to the facility will allow visitors to observe researchers working in the laboratory without requiring them to don clean room gowns, hairnets, and masks.

In addition to the nanofabrication wing, the AML contains two above-ground “instrument” wings and two “metrology” wings located 12 meters (40 feet) underground. It offers an unprecedented combination of features designed to virtually eliminate environmental interferences through tight simultaneous control of air quality, temperature, vibration, humidity, and electrical power quality.

NIST has invested in a complete suite of new equipment for the Nanofabrication Facility, which will be installed over the coming year. Among the equipment being purchased for the new facility will be reactive ion etchers, metal deposition tools, a focused ion beam, and numerous monitoring tools.

Once the new equipment is in place, NIST expects to open the facility for collaborative projects with researchers from industry and academia. By supporting a wide variety of metrology and standards research, this facility will build the technical infrastructure needed to advance the emerging fields of nanoscale science and engineering.

The facility is managed for NIST researchers by NIST’s Semiconductor Electronics Division.

Technical Contact: Eric Vogel, (301) 975-4723

Media Contact: Scott Nance, (301) 975-5776

A Safer Way to Make Metal Nanospheres

Tiny surface defects that form during processing can reduce the quality and yield of semiconductor devices, magnetic storage media, and other products. Inspection tools that locate, identify, and characterize surface defects based upon how they reflect or scatter light need to be calibrated with accurate particle size standards in order to work properly. Making metallic standards for such calibrations is typically a hazardous process, but researchers at the National Institute of Standards and Technology (NIST) and the University of Maryland have invented a safer method and apparatus for producing these standards.

Nanoscale spheres typically are used as size standards for calibrating surface inspection instruments. NIST produces a number of Standard Reference Materials (SRMs) used by the semiconductor industry for calibration purposes, including SRM 1963, which consists of 100 nanometer (nm) polystyrene spheres. The new method produces uniformly sized metal nanospheres, which might be used to determine, for example, whether surface inspection systems can differentiate metal contaminants from other defects.

The new method, patented earlier this year and licensed to MSP Corp., makes spheres 50 nm to 300 nm in diameter out of copper, nickel, cobalt, and other metals. The method involves generating aerosol droplets of a solution in an inert gas, and heating the droplets to form metal particles. The solution contains a metal compound, water, and a solvent such as methanol or ethanol. By contrast, the best of current production technologies use hydrogen gas as the solvent, posing a risk of fire or explosion.

The new method resulted from NIST efforts to develop and validate theoretical models for light scattering by polystyrene spheres. Because it is more difficult to predict light scattering by metal spheres than by polystyrene spheres, scientists validated their theories by making metal particles and measuring how they scattered light. This ensured that the models would be highly accurate for polystyrene. Scientists used metal particles made with the new method to validate their theories under a number of conditions and published several papers on the results. For example, they found that oxides grow on the particles at room temperature and limit their useful life as light scattering standards to only a few months.* This increases the value of having a safer way to generate the particles, because laboratories that use them may need to generate new batches of nanospheres on a regular basis.

* J.H. Kim, S.H. Ehrman, and T.A. Germer, “Influence of particle oxide coating on light scattering by submicron metal particles on silicon wafers,” Appl. Phys. Lett. 84, 1278, Feb. 23, 2004.

Technical Contact: Thomas Germer, (301) 975-2876

Media Contact: Laura Ost, (301) 975-4034

New Standards to Improve Measurements of Microdevices

Researchers at the National Institute of Standards and Technology (NIST), along with their colleagues at several companies, are completing experiments that validate new standards aimed at improving emerging new microelectromechanical systems, or MEMS, devices.

Microaccelerometers, the devices used to activate automotive airbags, are MEMS devices. In the future, microscopic MEMs devices made with gears and motors may, for example, be developed to clear blockages in arteries.

NIST scientists presented their findings at the semiconductor industry’s annual SEMICON West trade show, held July 12-16, 2004 in San Francisco.

Working with ASTM International, NIST has developed three new standards aimed at helping researchers measure more accurately several characteristics of materials used to construct MEMS devices. With more accurate measurements of microsystem materials, designers and manufacturers hope to improve the design and performance of these devices. Currently, laboratories measuring the properties of similar device materials produce widely varying results.

Each new standard is a set of procedures for measuring dimensions or a particular materials property. One standard advances the “in-plane length” measurement of a microsystem, or its length in one dimension, typically from 25 micrometers to 1,000 micrometers. A second standard would improve measurement of “residual strain,” or the strain the parts of a microsystem undergo before they relax after the removal of the stiff oxides that surround them during manufacturing. The final standard aims to improve measurement of the “strain gradient,” which determines the maximum distance that a MEMS component can be suspended say in air, before it begins to bend or curl.

Six companies have been collaborating with NIST on a so-called “round robin” experiment to validate the MEMS standards. The standards should reduce variations significantly in measurements between laboratories.

Technical Contact: Janet Marshall, (301) 975-2049

Media Contact: Scott Nance, (301) 975-5226

Lack of Supply Chain Standards Costing Billions of Dollars

Inadequacies in managing inventory, scheduling, and accounting information cost the automotive and electronics industries a combined total of almost $9 billion annually, according to a newly released study* commissioned by the National Institute of Standards and Technology (NIST). Almost all of these costs could be eliminated with optimally integrated systems for exchanging information throughout supply chains, the study concludes.

Conducted by RTI International (Research Triangle Park, N.C.), the analysis found that only a handful of firms are close to achieving “ideal” information integration with some or most of their supply chain partners. The lack of widespread interoperability costs the auto industry more than $5 billion a year and the electronics industry almost $3.9 billion a year, or about
1.2 percent of the value of shipments in each industry.

An underlying problem, according to the study, is the lack of universally accepted and implemented standards for the format and content of messages that flow between supply chain partners. This reduces opportunities for cost savings and leads to duplication of effort, maintenance of redundant systems, and investment in inefficient processes, such as manual entry of data when machine sources are available.

RTI defined excessive costs for several categories of logistics and accounting information flows, and it used case studies and Internet surveys to determine costs per occurrence for each category. These results then were combined with secondary data on sales, employment, and wage rates to estimate industry-level impacts.

The study is part of NIST’s strategic planning process for implementing the 2002 Enterprise Integration Act, which authorizes the Institute to help industry improve supply chain integration.

Technical Contact: Gregory Tassey, (301) 975-2663

Media Contact: Laura Ost, (301) 975-4034

*The report, Economic Impact of Inadequate Infrastructure for Supply Chain Integration, is available online at http://www.nist.gov/director/prog-ofc/report04-2.pdf (.pdf; download Acrobat Reader). Paper copies can be requested from Denise Herbert at dherbert@nist.gov.

NIST Helps Chip Industry Get Its Timing Right

Where does the time go? It’s a question we all ask ourselves. But for the microchip industry, keeping better track of time may translate into more efficient production processes, thus proving another old adage, time is money.

Researchers at the National Institute of Standards and Technology (NIST) are working with chipmakers to improve time synchronization and time-stamping systems used by the industry’s manufacturing equipment. Fabricating semiconductor devices involves a complex interplay of hundreds of different precisely controlled processes. Consequently, a critical factor in either diagnosing problems or improving production is knowing precise values for process parameters and matching the data up with exact moments in time.

But time-keeping and time-stamping of factory machines are not standardized. Some create a time stamp when they generate data, while others generate a time stamp when they transmit data to other machines. Still others never generate a time stamp at all.

Delays between data collection and time-stamping can vary from 100 milliseconds up to two minutes for different types of equipment. Currently, data are collected at a rate of about 300 values per second, while the goal is to collect 10,000 values per second with next-generation equipment. Time stamps will have to be accurate enough to distinguish and merge the influx of data from heterogeneous data sources.

Using their extensive expertise in timekeeping and time synchronization, NIST’s scientists are helping industry representatives systematically evaluate timestamping systems and identify ways to reduce errors. Working with International SEMATECH, they eventually hope to develop a standard to ensure uniform handling of time synchronization and stamping throughout the industry.

In addition, members of the Semiconductor Equipment Materials International (SEMI) standards organization plan to establish a time synchronization working group. The working group is looking for volunteers from industry to participate in the development of guidelines and standards.

Technical Contact: Ya-Shian Li, (301) 975-5319

Media Contact: Scott Nance, (301) 975-5226

Scaling Friction Down to the Nano/Micro Realm

An improved method for correcting nano- and microscale friction measurements has been developed by researchers at the National Institute of Standards and Technology (NIST). The new technique should help designers produce more durable micro- and nano-devices with moving parts, such as tiny motors, positioning devices, or encoders.

Friction measurements made at the microscale and nanoscale can differ substantially due to changes in applied load. In a series of experiments described by nanotribologist Stephen Hsu at a technical meeting held May 17-20, 2004 in Toronto,* NIST scientists confirmed that many of the measured differences appear to be caused by unintended scratching of the surface by the sharp tips used in making the measurements themselves.

The NIST team used a specially designed friction tester developed jointly by NIST and Hysitron Inc. of Minneapolis. A carefully calibrated force was applied to diamond tips having a range of sizes. Friction forces then were measured as each tip was slid across a very smooth surface of silicon. Friction at the macroscopic scale is usually straightforward—doubling the force between two objects produces twice the friction. However, work at NIST and elsewhere has shown that friction at the microscale does not always obey this scaling rule. Forces greater than about 2 millinewton** produced substantially greater friction values than expected.

Images of the test surface made with an atomic force microscope confirmed that unintentional scratching produced the extra friction. To correct for this effect, NIST researchers developed a way to measure precisely the size, shape, and orientation of the diamond tips so that friction forces caused by “plowing” can be subtracted to produce a more accurate final measurement.

Technical Contact: Stephen Hsu, (301) 975-6120

Media Contact: Scott Nance, (301) 975-5226

*The work was presented at the Society of Tribology and Lubrication Engineers annual meeting.
** For comparison, a penny held against Earth’s gravity produces a force of about 25 millinewtons.

‘Liquid Lenses’ to Improve Semiconductor Lithography

Two complementary systems built by National Institute of Standards and Technology (NIST) researchers for measuring the properties of “liquid lenses” may help semiconductor manufacturers wring new life out of current lithography facilities that use ultraviolet light to “print” components for microchips, as well as pave the way for “next-generation” production equipment.

Immersion lithography may be the key to improving image resolution beyond the current 90-nanometer (nm) threshold and shrinking chip feature sizes accordingly. By placing certain liquids between the final optical element and a silicon wafer, resolution could be extended to 45 nm for state-of-the-art lithography using the 193-nm wavelength of light, and possibly below for future systems using the 157-nm wavelength.

The method relies on the fact that use of certain fluids as the last optical element shortens the effective wavelength of light passing through the imaging system, thereby making it possible to produce smaller circuit features. The fluids need to have a high refractive index, among other properties. An accurate value of the index is essential because design requirements for all the optical elements are very tight.

NIST scientists previously improved measurements of the refractive index of water, which is almost 50 percent higher than air and could be used for 193-nm lithography. More recently, NIST measured the refractive index at 157 nm of several fluids commercially synthesized as candidate fluids for immersion lithography at the shorter wavelength. The fluids are made from hydrocarbons in which the hydrogen atoms have been replaced by fluorine to create more stable compounds. They have refractive indices near 1.4 at 157 nm.

NIST modified and updated old concepts to design the new systems* for measuring fluid properties at 193 nm and 157 nm. One is an automated facility designed for quick, moderate-accuracy surveys. Built with support from International SEMATECH, the method involves passing laser light through a sealed, temperature-controlled cell containing the liquid, and measuring the angle at which the light is deflected. Higher accuracy measurements at a slower speed can be obtained using a second approach that involves measuring the deflection angle of light passing through a liquid-filled prism.

Thanks in part to the reliable data produced by NIST, immersion lithography has been able to move forward into the development stage. At a recent conference organized by International SEMATECH, the consensus of industry leaders was that immersion lithography at 193 nm was likely to be the chipmaking technology of choice in the 2006-2009 time frame.

Technical Contact: John Burnett, (301) 975-2679

Media Contact: Laura Ost, (301) 975-4034

* Roger H. French, Min K. Yang, M.F. Lemon, R.A. Synowicki, Greg K. Pribil, Gerry Cooney, Craig M. Herzinger, Steven E. Green, John H. Burnett, and Simon Kaplan. 2004. Immersion Fluid Refractive Indices Using Prism Minimum Deviation Techniques. Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377 (SPIE, Bellingham, WA, 2004).

New Cryogenic Refrigerator Dips Chips into a Deep Freeze

In a major advance for cryogenics, researchers at the National Institute of Standards and Technology (NIST) have developed a compact, solid-state refrigerator capable of reaching temperatures as low as 100 milliKelvin. The refrigerator works by removing hot electrons in a manner similar to an evaporative air-conditioner or “swamp cooler.”

When combined with an X-ray sensor, also being developed at NIST, the instrument will be useful in semiconductor manufacturing for identifying trace contaminants and in the astronomical community for X-ray telescopes. The device can be made in a wide range of sizes and shapes, as well as readily integrated with other cryogenic devices ranging in size from nano-meters to millimeters.

A report of the work is featured on the cover of the January 26, 2004, issue of Applied Physics Letters. “The idea is to use a solid-state refrigerator for on-chip cooling of these cryogenic sensors,” says Anna M. Clark, the report’s lead author. “We have a working refrigerator that reduces temperatures low enough to be used with highly sensitive X-ray detectors. These detectors require subKelvin temperatures to minimize thermal noise and maximize their resolution.”

Current equipment capable of cooling to 100 milliKelvin is bulky and expensive. By combining an on-chip cooler with an X-ray sensor, the NIST device may reduce substantially the weight and cost of such equipment.

The refrigerator is made from a sandwich of nomal- metal/insulator/superconductor junctions. When a voltage is applied across the “sandwich,” high-energy (hot) electrons tunnel from the normal metal through the insulator and into the superconductor. As the hottest electrons leave, the temperature of the normal metal drops dramatically.

Technical Contact: Anna Clark, (303) 497-4409

Media Contact: Gail Porter, (301) 975-3392

Delving into Defects Spurs Prospects for Chip Insulator

A warm winter coat doesn’t work nearly as well if it’s full of holes. The same is true for hafnium oxide, a promising insulator for the next generation of smaller, faster microchips.While hafnium oxide prevents currents from leaking through the ultrathin layers of semiconductor chips more than 1,000 times better than conventional silicon oxide, its prospects have been dampened by too many current-draining defects.

A team of National Institute of Standards and Technology (NIST) and IBM researchers reported in the March edition of Electron Device Letters that they have quantified these “electrical capture defects” in a way that may help chipmakers reduce the defects or at least devise a way around them. NIST researcher John S. Suehle called the team’s measurements a “critical first step” for improving manufacturing processes.

Using a method called “charge pumping,” the NIST and IBM scientists found where the defects occur near the interface between the silicon substrate and the hafnium oxide and how those locations are ultimately detrimental to transistor operation. The method involves applying a voltage pulse and then measuring the current coming from a transistor. By changing the characteristics of the voltage pulse used, the scientists were able to measure the electrical-capture capacity of the defects.

Technical Contact: John Suehle, (301) 975-2247

Media Contact: Scott Nance, (301) 975-5226