The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design dcfifo0.v. The design dcfifo0.v has a depth of 128 words of 8 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.
The above waveform shows the behavior of the design under normal read and write conditions .
The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.