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Joseph J. Kopanski

Mr. Kopanski is an electrical engineer in the CMOS Reliability and Advanced Devices Group (683.06) in the Semiconductor & Dimensional Metrology Division (683) of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). He was born in Cleveland, Ohio in 1960. He received the B.S. degree in Applied Physics and the M.S. degree in Electrical Engineering and Applied Physics from Case Western Reserve University in 1982 and 1985, respectively. He joined the then National Bureau of Standards (now the National Institute of Standards and Technology), Semiconductor Electronics Division as an Electrical Engineer in 1985. At the NIST, his recent research has been directed towards developing quantitative metrology techniques based on scanning probe microscopes for semiconductor and dielectric characterization, including Scanning Capacitance Microscopy and Scanning Kelvin Probe Microscopy. In 2005, he served a term in the NIST Director's Program Office as a Program Analyst. Currently, he works in the Enabling Devices and ICs Group within the Semiconductor Electronics Division.

Joseph J. Kopanski

Position:

Electrical Engineer
Semiconductor & Dimensional Metrology Division
CMOS Reliability and Advanced Devices Group
Contact

Phone: 301-975-2089
Email: joseph.kopanski@nist.gov