Presentations from the 2003 International Conference on Characterization and Metrology for ULSI Technology

Because of the large interest in the talks given at this Conference and as a service to the semiconductor community, the organizers have made the slides from many of the talks presented available here. These slides should be considered the sole property of the speaker. Please do not alter or reproduce any of the slides presented.

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The Conference organizers would like to thank each of the speakers who have made their slides available!

• Critical Issues for Interconnects: Mechanical Strength and Adhesion Based on Nanoindentation
  Indira Adhihetty, Motorola
• Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices
  George A. Brown, International SEMATECH
• Overview of Optical Metrology for Ultra-thin Oxide and High-K Gate Dielectrics
  William W. Chism, International SEMATECH
• Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry Based on the International Technology Roadmap for Semiconductors
  Alain C. Diebold, International SEMATECH
• Status and Prospects for VUV Ellipsometry (applied to high-k and low-k materials)
  N.V. Edwards, Motorola
• Potential and Limits of Texture Measurement Techniques for Inlaid Copper Process Optimization
  Holm Geisler, AMD
• Difficulties and Challenge of Commercializing New Metrology
  Sam Harrell, Strategic Technology Advisors
• Semiconductor Technology Research, Development, & Manufacturing: Status, Challenges, & Solutions
  C.R. Helms, Past President & CEO, International SEMATECH
• In-line, Non-destructive Electrical Metrology of Nitrided Silicon Dioxide and High-k Gate Dielectric Layers
  Robert J. Hillard, Solid State Measurements
• Material Issues and Impact on Reliability of Cu/Low k Interconnects
  Paul Ho, University of Texas at Austin
• The "Ultimate" CMOS Device: A 2003 Perspective (Implications for Front-End Characterization and Metrology
  Howard R. Huff, International SEMATECH
• From the Lab to The Fab: Transistors to Integrated Circuits
  Howard R. Huff, International SEMATECH
• Direct to Digital Holography for High Aspect Ratio Inspection of Semiconductor Wafers
  Martin Hunt, nLine Corp.
• CMOS Devices and Beyond: A Process Integration Perspective
  Jim Hutchby, SRC
• Status and Future Prospects for Low K Interconnect Metrology
  John Iacoponi, International SEMATECH/AMD
• The CD-SEM - and Beyond
  David Joy, University of Tennessee, Oak Ridge National Laboratory
• Automated and Near Real-time, Trace Contamination and Chemical Species Analysis for the Semiconductor Industry
  H.M. 'Skip' Kingston, Duquesne University/Metara Incorporated
• Status of Non-Contact Electrical Measurements
  Valery V. Komin, Applied Materials Inc.
• Overview of Lithography: Challenges and Metrology
  Harry J. Levinson, AMD
• Interconnects, and Overview and Critical Review
  Kenneth A. Monnig, International SEMATECH
• Characterization of Si/SiGe Heterostructures for Strained Si CMOS
  Patricia M. Mooney, IBM
• TEM Overview and Challenges
  S.J. Pennycook, Oak Ridge National Laboratory
• In-Situ Metrology: the Path to Real-Time Advanced Process Control
  Gary W. Rubloff, University of Maryland
• Nanoscale Thermal and Thermoelectric Mapping of Devices and Interconnects
  Li Shi, University of Texas at Austin
• Characterization of Organic Contaminants Outgassed from Materials Used in Semiconductor Fabs/Processing
  Peng Sun, Intel Corporation
• Nanotechnology: A Look into the Future
  Thomas N. Theis, IBM Research
• Review of CD Measurement and Scatterometry
  Philippe Thony, ST-Microelectronics
• Advanced Mask Inspection and Metrology
  Nobuyuki Yoshioka, Selete
• Correlation of Surface and Film Chemistry with Mechanical Properties in Interconnects
  Ying Zhou, Intel Corporation