Summary:Atomic layer deposition (ALD) is increasingly being utilized to deposit the nanometer-scale, conformal layers that are required for many microelectronics applications, including high-k gate dielectric layers and DRAM dielectric layers. However, significant developmental issues remain for many of these applications. The utilization of Process models and in situ monitoring offers the potential to help solve some of these issues, e.g., by yielding insights that will enable improved efficiencies in film growth, in the development of deposition recipes, and in the design and qualification of reactors. The goal of this work is to provide validated, predictive ALD models and in situ diagnostics for ALD processes in an attempt to assist in solving some ALD developmental issues. Description:This work is intended to facilitate the efficient development and utilization of ALD processes. Significant process development issues remain for many ALD applications. Solutions to a number of these issues could be realized through the development of predictive models and in situ diagnostics for ALD processes. Technology computer-aided design, e.g., utilizing predictive process models, has been identified in the International Technology Roadmap for Semiconductors (ITRS) 2007 Edition as “one of the few enabling methodologies that can reduce development cycle times and costs.” [ITRS 2007 Edition, Modeling and Simulation, page 1] In addition, the 2007 ITRS notes that “a key difficult challenge across all modeling areas is that of experimental validation.” [ITRS 2007 Edition, Modeling and Simulation, page 2] Further, with respect to experimental validation, “One of the major efforts required for better model validation is sensor development and metrology, especially for models predicting the fabrication and behavior of ultra-thin films and ultra-fine structures.” [ITRS 2007 Edition, Modeling and Simulation, page 7] Hence, process models and in situ monitoring have the potential to yield insights that will enable improved efficiencies in film growth, in the development of deposition recipes, and in the design and qualification of reactors. Major Accomplishments:
Selected Publications
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Start Date:October 1, 2007End Date:ongoingLead Organizational Unit:cstlCustomers/Contributors/Collaborators:Nhan V. Nguyen, Semiconductor Electronics Division Staff:William A. Kimes Related Programs and Projects:Contact
James E. Maslar |