Daniel Josell

Dr. Daniel Josell joined NIST as a National Research Council postdoctoral researcher in the Metallurgy Division of the Materials Science and Engineering Laboratory. He became a permanent staff member in 1994. He has been Deputy Chief of the Metallurgy Division of NIST’s Materials Science and Engineering Laboratory as well as Leader of the Division’s Thin Film and Nanostructure Processing Group. He has also been a Technology Analyst in NIST’s Program Office and is author of more than 100 technical papers and one patent.

 

He has received the:

• Federal Laboratory Consortium Award for Excellence in Technology Transfer (1999) 

• Gold Medal Award of the U.S. Department of Commerce (2001)
• Samuel Wesley Stratton Award of the National Institute of Standards and Technology (2011)
  

Over the last decade his research has focused on advanced interconnects for microelectronics:

• Theoretical and experimental studies of superconformal deposition of metals in sub-50 nm wide trenches and vias
• • Received United States Department of Commerce’s highest award for copper interconnect related research as well as a US patent.
    
• First to explain and quantify superconformal electrodeposition and superconformal surfactant catalyzed chemical vapor deposition of copper and to demonstrate superconformal silver and gold electrodeposition and seedless processing for copper superfill.

His research has also covered the mechanical and thermal transport properties of multilayered materials as well as the thermodynamics of interfaces and their impact on the stability of nanoscale materials and structures. 

• Creep and tensile testing of multilayer thin films including study of capillary influences that affect their stability.
• Experimental and computational studies of solder joint geometries.
• Pyrometry and polarimetry studies of the rapid melting of refractory alloys.
• Determination of thermal transport properties of thin film and multilayer coatings at room and elevated temperatures.

Results for some efforts are given below (full details can be found in the literature).

3-d microstructured photovoltaics: Photovoltaic devices with interdigitated back contacts are shown below. They are fabricated using a single lithography step followed by a single electrodeposition step to create both p-type and n-type materials, in this case CdTe, as shown in the accompanying figure.

A study of the unique optical responses exhibited by such structures (below) with systematically varied geometries (e.g., electrode height, width and pitch) could be used to characterize the properties of materials and interfaces relevant to future nanostructured photovoltaic devices.

Superfill for interconnect fabrication: Images of trench superfill are shown below. They capture the unique bottom-up filling that has enabled damascene copper interconnects in microelectronics - these pictures are for silver superfill. The Curvature Enhanced Accelerator Coverage (CEAC) mechanism explains all aspects of superfill: from incubation period of conformal growth, rapid bottom-up filling, and overfill bump formation.

Exploding wire experiments and modeling - studies of alloy melting: Surface morphology of rapidly melted TiNb alloys near critical features of the melting plateau reflect solidus and liquid temperatures. The impact of grain size on local melting rate, and thus solute diffusion, is captured in rescaled data.

Thermal transport in multilayered films: Measurements using the "Mirage" technique enable measurement of thermal transport both in-plane and normal to the surface of thin film samples. These results showed the impact of decreasing the nanometer-scale bilayer thickness in Ti/Al multilayers of total thickness 3 micrometers.

Interpretation of these and other properties of multilayer thin films must necessarily consider their microstructure, including interfacial mixing as evident in TEM images and associated composition maps of some of the Ti/Al multilayers.