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Publication Citation: Back-End-of-Line Test Structure Design and Simulation for Subsurface Metrology with Scanning Probe Microscopy

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Author(s): Lin You; Emily Hitz; Jungjoon Ahn; Yaw S. Obeng; Joseph J. Kopanski;
Title: Back-End-of-Line Test Structure Design and Simulation for Subsurface Metrology with Scanning Probe Microscopy
Published: December 13, 2013
Abstract: As demands in the semiconductor industry call for further miniaturization and performance enhancement of electronic systems, the traditional planar (2D) electronic interconnection and packaging technologies show their difficulties in meeting the ever-advancing standards of the industry. To overcome such limitations, 3D stacked integrated circuits (3D-SICs) draw tremendous research interest and have been widely studied.[1] In the end, the billions of transistors are interconnected with tens of kilometers of wires that packed into an area of square centimeters, making a giant ,metallic forestŠ.[2-4] The complexity of the multi metallization levels of back-end of line (BEOL) brings challenges such as resistive-capacitive (RC) delay and reliability issues. From the metrology point of view, traditional scanning probe microscopy (SPM) technologies show mature capabilities of acquiring the surface metrology. However, additional capabilities such as subsurface imaging and electromagnetic property extraction in nano-scale are required to solve BEOL problems. Recently, several techniques, such as scanning microwave microscopy (SMM), electrostatic force microscopy (EFM) and Kelvin probe force microscopy (KFM) have shown their promising capability of subsurface characterization on different semiconductor devices. [5, 6] To enhance our SPM subsurface metrology capabilities and determine more accurately the limitations of the technique, we will compare experimental and simulation results. A multi-level test chip with several well-known buried structures has been designed and will be integrated on a thumb-nail size chip. Pads will be bonded on a printed circuit board (PCB), allowing external bias accesses. Different feature components can be biased separately to simulate a device under test (DUT). In this work, the surface potential distributions of opposite biased parallel buried metal lines are simulated to estimate the KFM subsurface resolution under different line depth
Conference: 2013 International Semiconductor Device Research Symposium
Pages: 1 pp.
Location: Bethesda, MD
Dates: December 11-13, 2013
Keywords: BEOL, KFM, SMM, Subsurface metrology
Research Areas: Semiconductors, Microelectronics