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Publication Citation: DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY

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Author(s): Lin You; Jungjoon Ahn; Joseph J. Kopanski;
Title: DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY
Published: March 25, 2014
Abstract:
Proceedings: 2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics
Pages: pp. 203 - 205
Location: Gaithersburg, MD
Dates: March 25-28, 2013
Research Areas: Nanotechnology, Nanoelectronics and Nanoscale Electronics, Atomic force microscopy (AFM)