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Publication Citation: PWB Warpage Analysis and Verification using an AP210 Standards-based Engineering Framework and Shadow Moire

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Author(s): Dirk Zwemer; Manas Bajaj; Russell Peak; Thomas Thurman; Kevin G. Brady; S McCarron; A Spradling; Mike Dickerson; Lothar Klein; Giedrius Liutkus; John V. Messina;
Title: PWB Warpage Analysis and Verification using an AP210 Standards-based Engineering Framework and Shadow Moire
Published: March 10, 2004
Abstract: Thermally induced warpage of printed wiring boards (PWB) and printed circuit assemblies (PCA) is an increasingly important issue in managing the manufacturing yield and reliability of electronic devices. In this paper, we introduce complementary simulation and experimental verification procedures capable of investigating warpage at the local feature level as well as the global PCB level. Simulation within a standards-based engineering framework allows efficient introduction of detailed feature information into the warpage model. Experimental results derived from temperature-dependent shadow moir¿ provide a rapid high resolution picture of local warpage in critical regions. We describe these results for two unpopulated PWB test cases.
Conference: EuroSimE 2004
Proceedings: 5th International Conference on Thermal, Mechanical and Thermo-mechanical Simulation and Experiments in Micro-electronics and Micro-systems
Pages: pp. 121 - 132
Location: Brussels, BE
Dates: May 11-13, 2004
Keywords: Analysis;AP210;Framework;Multi-Representation Architecture;Phase Stepping;Shadow Moire;Standards;STEP;Warpage
Research Areas:
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